The Design And Implementation Of PSMC And Rapid DMA For Multi-core DSP

With the widely using of DSP in the embedded field,the single-core DSP failed to meet the requirements of large-scale computing, which makes the gradual development from single-core DSP to multi-core. How to quickly supply the data for the multi-core DSP is one of the problems which urgently need to be solved. For this problem,the design of the parallel shared memory architecture is one of the crucial technologies and the DMA is transplanted into the DSP core to change the traditional data interaction, so the performance of multi-core DSP is improved greatly. A high-performance floating-point multi-cores DSP chip — X_DSP is designed independently by my school. The design of PSMC and IDMA in X_DSP is the major task,and the main content is as below.1.The design and implementation of PSMC has been completed. The design improves the performance of PSMC as the goal by decreasing decrease the delay of the communication between the multi-core. The pipelining technology is applied for DSPx L2 interface with the high data throughput rate to achieve continuous reading and writing without blocking. The memory bank partition technology is applied for the memory array. Each bank has a separate data bus and uses mixed addressing mode of continuous and cross addressing to reduce the accessing conflict rates. For the bandwidth management,the arbitration strategies of the configured priority and time slices rotation are applied to ensure the quality of data accessing service. The double lock structure is adopted to protect memory,which enhances the security of the shared memory and external memory.2.The design and implementation of IDMA has been completed. Based on the X_DSP architecture requirements,IDMA supports the dual-channel operation. The arbitration strategies of the configured priority and token rotation meet the balance conflicts of the dual-channel concurrency accessing,and take account of the fairness of another requests. Because of the slow transferring caused by the disconnected address,a strategy of packet and pipelining is proposed to effectively increase the transferring speed. Based on the data-transfer size formal,a dual-buffer structure is adopted to reduce the chip area in the IDMA. In addition,the datas should be filtered when the buffer is written to avoid invalid data written into it,which reduces data toggle and dynamic power consume.3.The verification and logic synthesis of PSMC and IDMA have been completed. The verification is to ensure this design correctness,the method of hierarchical verification is applied including the module-level verification,component-level and system-level verification,the coverage guarantees the completeness of verification in hierarchical verification. The PSMC and IDMA are compiled based on 45 nm standard cell library in logic synthesis. For the critical path problem in logic synthesis,it is optimized by adjusting the pipelining station,which solves timing violation,the synthesis constraints and options are adjusted repeatly for the optimized area to ensure the compiling requirement,total area of PSMC reduces 23.60%,the total area of IDMA reduces 14.40%. The design meets the requirements of X_DSP that PSMC works properly at 500 MHz clock frequency and IDMA works properly at 1GHz clock frequency,the design achieves the expected goals.