The Design And Verification Of Enhanced Direct Memory Access Controller On DSP64X

The topics is from a 32-bit high-performance digital signal processor chip (DSP64X),which is designed by institute of Microelectronics in National University of Defense Technology. The work frequency of the chip is 400MHz. In the chip, enhanced direct memory access (EDMA) controller is the core of data transfer control. Therefore, how to improve the data transmission speed of EDMA and how to design an efficient EDMA controller become the core of this paper.By analyzing the internal structure of DSP64X and the transmission principle and performance requirements of EDMA controller, this paper researched and designed EDMA following three areas to improve the data transmission speed:In the data transmission protocols: This paper proposed burst and non-burst combined transmission, in the burst transmission, a read or write command can transmit much data. This paper also extended the interface of devices that are visited frequently to 64-bit, supporting 64-bit transmission. In addition, this paper configured special data transmission buses for high-speed devices.In the structure of EDMA: This paper designed read and write buses separated structure, which is called "double bus" architecture. In the queue registers, every transfer request is subdivided into read requests and write requests. Read requests are controlled by read transfer state machine, write requests are controlled by write transfer state machine. This paper also designed separate source Pipeline, destination Pipeline, read command buffers and write command buffers, all these modules can work in parallel, creating the conditions of read and write operations execute concurrently.In the transmission mechanism: This paper proposed and designed a new transmission mechanism, which can make read and write execute concurrently. This paper also designed pipeline to deal with read and write operations. In the command buffer, every port has a read pipeline and a write pipeline, the read pipeline is subdivided into four pipeline segments, the write pipeline is subdivided into three pipeline segments, all of the pipelines can run simultaneously, the data is passed by data bypass way. The transmission mechanism can implement the parallelism of many transfer requests besides of the parallelism of read and write.Finally, this paper designed the EDMA controller successfully and mainly used software simulation and hardware simulation combined method to verify the all function and timing of EDMA. Verification results show that the EDMA can work properly and stable. Then, this paper compared the performance of our EDMA and the EDMA of similar Mainstream high-performance chip (DSPx), the results show that the data transmission speed of our EDMA is similar with the speed of DSPx's EDMA. Therefore, our EDMA improves the performance of DSP64X system. This paper completed the expected research and design tasks.