Research And Achieve Of High Level Synthesis For Multicore Digital Circuit

With the rapid development of FPGA, more and more logic gate arrays are integrated into single chips. However, with the greater complexity of designing in the low-level hardware description language(HDL), such as Verilog and VHDL, it is easy to get wrong and hard to locate the right position and, as a result, hardware design for many applications, is much more difficult and expensive. In addition, it is not easy to estimate the time when the product can be launched in the market. As regards software, it is easy to debug the system and correct any errors because a great number of mature debugging and analysis tools can be obtained free. In comparison, hardware works much faster and much more efficiently than software but High Level Synthesis(HLS) not only has the advantage of software – it is easy to operate, but also the advantage of hardware. Thus HLS has become an important research factor in hardware circuit design.In this paper, we use the retargetablity of the LLVM(Low Level Virtual Machine) compiler framework to design a qualitatively high-level synthesis tool- C2 Verilog compiler. The system can automatically transform C-programme into a register-transfer-level(RTL) hardware description language. First, the paper made a detailed analysis and presentation on the structure of LLVM, and based on these, it proposed the design content and research direction shown in this article.The main work and conclusions of this paper are listed as follows:(1)Research on how to transform multicore software technology into multicore hardware circuit. By using the feature of Clang compiler front-end(support for OpenMP), we can implement multicore software technology. The LLVM intermediate representation code which is generated by the Clang compiler front-end is made up of basic blocks. Therefore, this paper suggested using the block-level parallelism extraction technique to make be unrelated between each basic block of the LLVM intermediate representation code. Finally, the function of multicore hardware circuit which is generated by code generator back-end is correct, and the circuit’s performance was found to have improved greatly.(2)Achieve pipeline function. In this paper, we use the scheduling module technology to analysis the data dependence graph(DDG) of the LLVM intermediate representation code. Making the instructions classification and obtaining the schedule for the pipeline stages depends on their relationship. According to DDG, we can get the related distance between all pairs of instructions. Then we can optimize the level of the instructions again by using distance information. Finally, after that the initiation interval of the pipeline must be obtained, to make the functions come true. By using functional simulation, we used pipeline technology processing parts of C program to improve the performance about 33.6% ~ 52.1%.(3) Achieve code generator back-end of C2 Verilog system. Based on the analysis of the LLVM code generator back-end, we obtained the main features of this code generator back-end design, including the modification of the description information of the whole system, achieving workflow of code generator which is composed of each sub-function modules, and how to modify the configuration information of the whole C2 Verilog system to operate normally. We finally completed the design of the code generator back-end for this system by using this information.