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Code Transformation-based High-level Synthesis Optimization Method For FPGA And Applications

Posted on:2018-12-24Degree:MasterType:Thesis
Country:ChinaCandidate:L MaFull Text:PDF
GTID:2348330542981077Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
With the improvement of the IC design scale and the application complexity,the abstraction of the EDA's automation design tends to be more and more high-level.More and more High-Level Synthesis tools have been applied,especially for FPGA development.High-Level Synthesis is a tool that efficiently translates high-level languages into register-transfer-level descriptions that satisfy design constraints.High-Level Synthesis tools improve the hardware design abstraction level,reduce the hardware design time,shorten the time to market,reduce the difficulty of hardware development and communicate two areas of software design and hardware design.Therefore,High-Level Synthesis tools are considered to be the core role of the next generation of semiconductor industry,receiving more and more attention in business and academia.High-Level Synthesis tools automatically optimize the design when they synthesis the input design,but they are limited to the specific code structure and require some constraints.In order to get a good performance of the circuit design,input design needs to be modified to improve the efficiency of High-Level Synthesis tool optimization.In this paper,the code transformation method is presented to optimize the input design and proposed several optimization programs which can effectively improve the optimization efficiency of the High-Level Synthesis.By means of data replication,ping-pong structure,function creation,loop unrolling and loop pipelining,the dependence of data is solved and the degree of parallelism is improved.The method proposed in this paper is applied to the development of Blokus Duo and quasi-Newton algorithm.For the Blokus Duo experiment,the optimization method proposed in this paper can improve the running speed 14 times,and the performance is similar to the RTL designs.For the quasi-Newton algorithm,the neural network model of 3-8-1 is 16.6 times faster than the software design,and the speed of 3-8-1 is better than that of RTL after the optimization method is applied.
Keywords/Search Tags:High-Level Synthesis, FPGA, Code Transformation, Accelerate
PDF Full Text Request
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