The Improvement Of Algorithm For The High-Level Synthesis Of Designs With Complex Control Flow

With the developing of integration technology and improvement of integration degree, the process of Integrate Circuit Design have been becoming more complicated, and traditional logical design have not satisfied the needs of design. Thus high-level design measures need to be used to meet those requires. High-level synthesis is the most prominent in these high-level design measures. After used of high-level synthesis the performance of design was improved obviously and the period of design was distinctly short.High-level synthesis is the one of the key technologies in EDA and it becomes more and more important in circuit design. In the first part of this paper, we describe the development of EDA and high-level design automatic. Also the chief problems of high-level synthesis system are expounded in the paper and narrate the significance of the topic.In this paper I mainly mend the HLS system Spark to improve performance of design with complex control flow. Firstly, banding dynamic CSE is combined with condition speculation to move operation. Using this further exposed the algorithmic parallelism. Secondly, the quality of synthesis result is improved by mending Priority-based Global List Scheduling Heu-ristic. Finally code motion and compiler transformation can lead to steering logic and interconnect. Thus it can increase the circuit areas and power consumption. In the Spark high-level synthesis framework there are a method for area optimization by reducing interconnect. But it can't control the power consumption. Furthermore interconnect in the form of multiplexer networks may consume more than 40% of the total power of a control flow intensive circuit. So in this paper we introduce a new RT level technique that targets multiplexer trees and restructures them to reduce power consumption.