The Design And Implementation Of1GHz Add And Shift Unit Of X-DSP

Digital Signal Processor (DSP) is a kind of chip that realize real-time processingfor signal and image. It has high efficiency,low power consumption and low costfeatures. With rapid development of DSP, It is widely used in many fields, such ascommunication technology, military application, family electricity and so on. In themeantime, higher performance DSP is also required for more and more applications.X-DSP is a32-bit high performance DSP being designed and belongs toindepended positive design. It has very powerful operation ability to realize manyfixed-point and floating-point operations. Its architecture is VLIW and it adopts SIMDtechnology. It is bound to run at a frequency of1GHz. ASU Unit is a main executionunit for fixed-point and floating-point operations in X-DSP. In this thesis, we deeplyanalyze and reaserch the instruction function of the ASU Unit in X-DSP, then, designand realize it. The main research of this topic is as follows:Firstly, from the overall design of ASU arithmetic Unit, designed hierarchical on itaccording to the Standard-Cell-Based method, and Implemented a shifter for the criticalpath combining with the Full-Custom design method.Secondly, in-depth studied the architectural design of the ASU Unit, rationallydivided it into small segments, and described the design method and their benefits ofeach functional modules and key components used in the logic design.Thirdly, simulations were carried out to verify the function of the prepared RTLcode, developed test vector of ASU arithmetic unit, and combined with the verificationmethod of FPGA, added to verify the object design, fully guaranteed the functionalcorrectness.Fourthly, Some important aspects should be considered in the logic synthesis indetail, and according to the characteristics and requirements of the design, used avariety of optimization strategies to optimize the object design. A comprehensivecomparison scheme is implemented by many kinds of different modules, finally chosenthe appropriate method to design the ASU unit.In the end, under the worst case, using the Design Compiler of Synopsys in a45nm CMOS process, ASU Unit achieves satisfied result in timing, area and power. Thefrequency is up to1GHz, the area is63709.329829um2, the dynamic power and theleakage power are10.5928mW and1.6359mW in each.