TSV Power Model And3D NoC Power Consumption Analysis

To continue the progress of Moore’s law,3D integration and Network onChip(NoC) are introduced. Three-dimensional IC is a way to improve density oftransistors on a chip and TSV is considered as one of key technologies in this process.NoC can supply a more effective way to transfer data than bus structures in systemswith more and more IPs. These two innovations were founded and then connectedspontaneously, coming up with the concept of3D NoC.The paper introduces these two technologies. Building the power consumptionmodel of TSV is the first step, then this model is embedded in a2D NoC powersimulation software, After this step, we used this software to simulate powerconsumption of2D and3D NoC. In detail, first, the equivalent circuit and electricalparameters were extracted and analysed. Second, the capacitance model is built andsimulated by Silvaco. Last, this model is embedded in OPNEC-SIM, and then we usethis tool to simulate2D and3D NoC with sharing L2cache.The simulation results of Silvaco indicate that: Capacitance of TSV can beapproximated as minimum depletion capacitance when TSV work in the range of0V to5V. This model matches with results of simulation accurately, for example, the errorbetween calculation and practical measurement is10.1%, and the error betweencalculation and simulation value is6.9%. The simulation results also indicate thatcapacitance is almost invariant when TSV work in0V-1V, so minimum depletioncapacitance can be used to calculate power consumption.The simulation results of OPNEC-SIM with the TSV power consumption modelindicate that: Power consumption of3D NoC is less than2D NoC under the sameinjection rate and3D NoC with two cache layers is least. For example,20.2%and31.1%power consumption can be reduced under the0.3injection rate by adopting twokinds of3D mesh NoC, respectively.