Research On Power And Delay Model In High-Perfomance Low-Power NoC Design

The high-performance low-power network-on-chip (NoC) design is a trade-off between performance and power cost, the design goal is to utilize the power of NoC to attain high performance as much as possible. In order to enable performance and power exploration at system level, the designers need to use high-level power and delay model to evaluate the power cost and performance in system-level design.The main issue in this paper is modeling the power and delay of NoC based on the RTL level communication components for system level performance and power consumption evaluation. Fistly, we introduce the communications related to the power and delay model, and then improve the performance and implement the OCP read operation for network interface. Secondly, we apply macro-modeling for energy model extraction of the NoC with higher accuracy to overcome the shortcoming of existing architecture-level power simulators. On the EDA platform of Synopsys, using 180nm technology, we compare our power model to gate level analysis by PrimeTime PX. Experimental results show that the mean absolute power estimation error of the power model is 5.2% against a gate level simulation with 600 times speed up. Thirdly, we use M/G/1 queuing system to modeling the delay of NoC, and then propose an algorithm to calculate the network latency of an application run on NoC based on backward algorithm. The comparison between the delay model and simulation results shows that the analysis approach with average error of nearly 8% achieves a speedup of 250 times.Finally, the power and delay model is applied to system level design of H.264 decoder based on NoC. We divid the tasks into sub-modules ant evaluate the power and delay of decoder using different mapping strategy.The simulation results and the examples of applications show that the power and delay model proposed in this thesis can provide accurate and efficient evaluation platform for system-level design of NoC.