10 G Epon System Oam Sublayer Of Logic Design And Validation

This paper describles the design and verification of10G EPON OAM sublayer logic. Firstly, it introduces the Ethernet technology, access technology, the development course of PON technology, as well as the working mechanism and relevant theoretical knowledge of the10G EPON system; followed by an ESL modeling of10G EPON OAM sublayer; and then focuses on the logic design and verification of10G EPON OAM sublayer. Detail ESL modeling analysis is given to such Units as Control Unit, Multiplexer Unit and Parser Unit, which are provided by agreement IEEE802.3ah and IEEE802.3av. As for function modules in whole OAM sublayer’s hardware logic, such as configuration module, downlink data frame processing module, CPU OAM frame processing module, downlink information OAM frame automatically generated module, scheduler including RR scheduling and SP scheduling module, downstream data flow control module, uplink frame analysis module, uplink data frame processing module and upstream OAM frame processing module, they are all given detail design and simulation. In the end, designed10G EPON OAM sublayer logic collaborated with corresponding software successfully achieves all the features of10G EPON protocol standard specification.In the system design, each module is designed by using top-down design process. Firstly, IEEE802.3ah and IEEE802.3av agreement are given a comprehensice analysis and research, and then each module’s requirement specification is worked out after considering user’s product demand book. Nextly, according to the logic requirement specification, entire system features are given overall program design. Subsequently, the OAM sublayer’s ESL modeling is completed so as to ensure that system function and performance can be achieved. Finally, it is time to complete detail program design and RTL coding of each sub-module in the system.In the system verification, the taken verification strategy is from module to system. Sub-modules at all levels are tested firstly. After each module’s function has been guaranteed fully, it is time to do integration verification. Lastly, verification for whole10G EPON system is done. Through the verification of all integrated business functions (registration, cancellation, MPCP process and dynamic bandwidth allocation, etc.), entire10G EPON system functions can be achieved and the compatibility between various hardware and software modules can be ensured.Finally, under the premise of adequate and reliable EDA simulation for10G EPON system, synthesis and layout are done to system’s logic part. Above work has provided guarantee for tapeout of the10G EPON ASIC.