Design And Research Of 3G-BERT Based On FPGA

The Bit Error Rate tester is an important testing-equipment in system test instrument communication,commonly used in the network of optical fiber communication and mobile communication. It has a vital role in using these BER testers to analysis network problems for technical support staff maintenance network. This paper studies on FPGA technology, adopting the pseudo random signal source, testing 3G networks in CPRI interface, and the rate can reach to 6.144 Gbps.The artical describes 3G BERT instrument sending and receiving module, including the basic principle and design schemes, and designs the pseudo random signal generator below interrupting communication. At the same time we use the FPGA technology to design the 1st CPRI protocl to test the physical layer and CPRI layer 2 data link layer of synchronous with K28.5 signals, realize the data synchronization and one-to-one data, then complete the number of error in data coding with 10 bitwidth of data in every 800 data, it will pass encoding data through the SPI interface to AT89S51.According to characteristic of pseudo-random source, we analyze its codes characteristics and data stream implemented, and use the advantages of data, at the same time according to different network analysis of different error test method to the device's influence. Every modules of the paper including pseudo-random code generator, synchronous frame insertion and testing, 8b10b codec with string and conversion, data comparison sysytem in Verilog code simulation showed that using MCU software completed in protel serial port module and minimal systems. Upon completion of all of the modules on the BERT the sender and receiver respectively is simulated, and the delay in 10ms at the sending part delay in 20ms at the receiving part.