Bit Error Rate Tester Based On FPGA

BERT (Bit Error Rate Tester) is an essential testing device in performance testing and malfunction diagnosis for communication system. It is used in detecting for reliability of a communication system.It is an important instrument which can verify the data transfer quality.The traditional design about BERT is based on CPLD.The disadvantages of traditional design are complicate structure, high price and hard to taken. With the development of EDA technology nowadays, more and more functions will be integrated on one chip by hardware engineer. This paper analyzed the design requirements of BERT based on FPGA, and made a scheme that uses FPGA as the main chip in the system.The structure of the board is star-type.This paper brought forward integrating diagnosis function modules on FPGA, improved the system's integration and extend ability, and all the function modules can be designed and modified in RTL level.This paper researched the work theory and structure of traditional BERT, and used VHDL program language to realize a majority of BERT functions on FPGA.There are mainly 2 part designs in this paper, hardware design and software design which based on FPGA. The hardware design is mainly about the circuits around FPGA, CPU and the interconnection of them. The software design is mainly about using VHDL programming language to realize some functions like 10/100/1000MHz 3 level speed control,5 code type to choose such as 9,11,15,23,31 and some other resource control around FPGA, etc.The design mainly focuses on a single FPGA chip, it contains many functions, integrated generating and receiving, having statistics for and calculating the test code as a whole. With a little exterior assistant circuit, the whole BERT system can be made, so the size, weight and cost of BERT can be cut a lot.This paper finished the BERT demo system at last, including the BERT demo board and the BERT core based on FPGA, and could do some BERT basic functions. The whole hardware cost was cheap; it proved that the BERT system design based on FPGA is effective and reliable.