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Study And Implementation Of Instruction Scheduling For Configurable Tta Compiler

Posted on:2011-06-10Degree:MasterType:Thesis
Country:ChinaCandidate:Z H WangFull Text:PDF
GTID:2198330338989195Subject:Computer system architecture
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With the development of ASIC design and the increasing complexity of the general-purpose processors, the demand of embedded chips with high performance, low power and short to market is becoming more and more urgent in current society. However, design automation tool chain development for high performance configurable processor is a big challenge. Design an effective compiling system is the important part of the design automation tool chain and the flexibility of the configurable processor architecture has higher requirements in the compiler design. TTA (Transport Triggered Architecture) is a flexible, configurable, simplified in hardware design and receives more and more attention in the industrial community.This thesis does some research work of some optimized algorithms in the compiler backend, constructs an optimized framework of instruction scheduling for TTA processors within the platform of the machsuif compiler which is developed by Stanford University. This thesis does many works like resource allocation, configurable compiler design and software bypass in different stages to optimize the Intermediate Representation (IR). Proposes and implements a heuristic instruction scheduling algorithm based on minimum latency to schedule the sequential TTA code. The algorithm establishes a programming model that can convert the instruction scheduling into a search of the optimal coding and introduces minimum-latency adjustment methods (critical path based adjustment and its improving method). In the last, the Genetic Algorithm helps to achieve the implementation of this algorithm. The conflict of resource and pipeline, deadlock of scheduling which are faced in the List Scheduling algorithm can be properly solved in this algorithm. Experimental results show that the algorithm has significant performance gains over List Scheduling. It has a higher ILP than List Scheduling over 90% of the DSP-specified benchmarks. In addition, the improved adjustment method has slightly better result than critical path based adjustment method in the average ILP over the benchmarks.
Keywords/Search Tags:Configurable Processor, Transport Triggered Architecture (TTA), Instruction Scheduling, Heuristic Search, Compiler's Optimization
PDF Full Text Request
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