Design And Optimization Of Instruction Scheduler For Tiled Processor Architecture

As the development of the semiconductor technology and computer architecture technology,Tiled Processor Architecture(TPA) becomes a direction of multi-core processors. Tiled processor effectively solves the wire delay, power consumption, scalability, and many other problems that modern processors face. Tiled processor architecture implements a global control flow and local data flow combined computing model, which divides the program into many hyperblocks. A hyperblock is a program structure having a single entry and several exits. There are control dependences among hyperblocks. To explosive the instruction level parallelism, we take over control dependences with data dependence inside the hyperblock. As an important component of compiler system, instruction scheduler is the key of improving procedure performance. This dissertation focuses on designing and implementing an instruction scheduler for a tiled processor TPA-PI, including how to map instructions onto the chip, how to use software abilities to manage the computation and storage resources on the chip.The major contributions of this work are as follows: (1) Design and implement an instruction scheduler for a tiled processor TPA-PI. TPA-PI instruction scheduler takes hyperblock as a unit and maps the block onto the TPA-PI processor execution array. It takes TPA-C as input, output assembly language TPA-S. (2) Analysis several factors with quantitative approach. These factors can affect the performance of the procedures. We can improve the heuristics functions of instruction scheduler with the results. We take critical path, load balance, data locality, register instructions, anchor point instructions, weighted path, average path and on-chip network as analyzed factors. (3) Propose an instruction scheduling algorithm based on heuristics functions, raise two heuristics functions: AVBLON and ARBLON, we take anchor point instructions(A), average path(V), load balance(B), data locality(L), register instructions(O), on-chip network(N) as parameters of heuristics function. Experiments show that AVBLON instruction scheduler improves the performance 28%, compared with a greedy instruction scheduler. To modify the drawback that AVBLON instruction scheduler needs profiling information, sometimes we use average path instead of weighted path.The work in the dissertation provides an available instruction scheduler for TPA-PI, which can be used for exploding instruction level parallelism. Plus, experiment results can guide designers of the processor and compiler to improve the compiler system and the Architecture.