Research On Instruction Scheduling For IA-64

With the development of computer technology, it is the tendency that the responsibility of achieving high performance is transferred from hardware to software. As basic system software, compiler becomes more and more important. In modern computer architectures, instruction scheduling is one of the most important compiling optimization, and influences the improvement of computer performance deeply. At the same time, instruction scheduling is very complicated and full of challenge.It is the character of IA-64 architecture to improve computer performance by depending both on compiler and hardware. IA-64 architecture provides rich features to support the exploitation of instruction level parallel (ILP). With the application of Itanium family processors, the realization of IA-64 architecture, on high end servers, it becomes a focused project to obtain high performance by instruction scheduling.We do researches on instruction scheduling taking IA-64 architecture as the target platform. Firstly, we analyze how to exploit ILP from program semantic aSPECt. By studying popular instruction scheduling techniques and comparing their characters, we put forward a model of instruction scheduling based on scheduling regions.Then we analyze technical characters of IA-64 architecture and eSPECially focus on the characters to which instruction scheduling relates. After we study instruction scheduling procedure of GNU Compiler Collection (GCC) compiler for IA-64 architecture and compare it with the counterparts of Intel commercial compiler and Open Research Compiler (ORC), we indentify key factors of instruction scheduling on IA-64 architecture. Finally, we indicate the merits of GCC instruction scheduling procedure, and analyze the points where improvement is necessary, and put forward an amended instruction scheduling algorithm. The experiment results show that the amended algorithm can improve code size and obtain better performance.