FPGA Design Of MPEG-2 Video Decoder

MPEG-2 standard was established for higher industry standard of picture and higher transport rates by Moving Picture Expert Group. The standard is so excellent that it becomes the most influential standard since ten years ago, and is still one of the most important compress standard nowadays .The research content of thesis is the standard of MPEG-2 video. Firstly, the total system architecture of MPEG-2 video decoder was introduced; then design of the FPGA prototype and its verification were achieved; at last, in the SMIC 0.18μm standard cell CMOS technology, the decoder is implemented targeting ASIC. The contributions of the essay are summarized as following:1. The architecture design of MPEG-2 video decoder is implemented. With Top-Down method, the decoder system was divided into some sub-modules; based on the characteristic of video decoding, define the control method of system; divide the video datas into intra-data and inter-data, then the two kinds of data was decoded by parallel algorithm.2. the design of sub-modules: according to the system design ,the parser module was designed by a unique method; In the VLD module, taking the advantages of both combinational logic and LUT, accomplished the decoder of variable data, reduce the decoding time obviously; IQ,IDCT module was designed by pipeline method, also reduce the time of calculating heavily; For the motion compensation is the most intensive part of accessing memory and has high throughput, several methods were adopted to improve memory access efficiency, including four pixel interpolator, pixel buffer augmentation, and parallel architecture, which lead to good speedup of motion compensation.3. Based on the software reference program, functional verification is carried out by comparing the simulation results with the output results of software. At last, the FPGA prototype is implementated based on the developing board EP2S180 from Altera. FPGA prototype based verification showed that the design gets satisfactory decoding effects.The design was described with Verilog HDL. It has been implemented by Field Programmable Gate Array (FPGA). Synthesis was also fulfilled with Synopsys Design compiler, based on SMIC 0.18μm standard cell CMOS technology. Demo experiment with real video stream shows that the design can meet the real-time decoding requirements of the MPEG-2 MP@ML video sequence.