The Optimization Of MPEG4 Video Decoding System Based On SOPC

The rapid development of Multimedia Technology promote a large number applications of digital image processing, where the handheld terminal is the main target of digital image processing operations. The digital video images have large amounts of data, which have contradiction with the current storage media and communications transmission media. One way to deal with this contradiction is to compress. There are many compression standards, and this paper only focuses on the MPEG compression standards. In order to bring out the video decoding system, after comparison and analysis, we decided to choose the plan which based on SOPC technology.Chapter 2 mainly introduces the MPEG-4 standard of the MPEG family of compression standards. As the advantages of the highly efficient encoding and content-based encoding, MPEG-4 is very suitable for this paper. MPEG-4 is also the trend of digital compression standard developing. As the different MPEG-4 Profile for different video processing operations, we choose Advanced Simple Profile (ASP) which is fit for this paper's applicational purpose. By the description of MPEG-4 ASP video codec process, we can design different modules to achieve the MPEG-4 ASP video decoding system.Since chapter 3 we begin to design the system. First of all, we introduce the SOPC technology and its development status, and highlighted why we choose the design based on SOPC:powerful, highly integrated, low power consumption, easy to use. Also we introduce the NiosⅡembedded soft-core of SOPC system which is chosed in this paper. And then we begin to introduce the Altera's DE2 experimental platform:we start with DE2's development environment, and then introduce the SOPC development process, and finally introduce the NiosⅡbus interface specification-Avalon bus. We begin to design the MPEG-4 video decoding system, that the system is divided into four modules:video data input/output, video decoder, YUV-RGB color converter and the VGA display module. After the detailed design and construction of the four modules, we begin to use the QuartusⅡto integrate the system. The Quartus II's SOPC Builder can customize the system and generate circuit diagrams, and then we can use the ModelSim to simulate and debug, that a MPEG-4 ASP video decoder system is achieved. By the Statistical functions of the software, we can get the average decoding rate of CIF (352×288) less than 15 frames per sec. This experimental results is not very well. The decoded video image can not play in the handheld terminal. So, we need to improve this system.Chapter 4 describes how to improve the MPEG-4 ASP video decoder system. By the help of GNU's gprof, we get the data of the proportion of that each module occupy the CPU resources when the video decoder runs. We can see that we must replace some of the cumbersome and complex software operations with the remaining resources of FPGA, which can speed up the CPU and increase the decoding efficiency. This is the hardware acceleration theory. After carefully analysising and considering, we decide to optimize the YUV-RGB color converter,2D-IDCT and motion compensation (MC).First we introduce a concept of Distributed Arithmetic (DA), which can optimize the YUV-RGB color converter and 2D-IDCT by leading DA into the algorithm of both modules. We also improve the motion compensation module on the algorithm and hardware, which improve the operation rate of CPU. Now we begin to integrate the optimized MPEG-4 ASP video decoder system, and we get the data of average decoding rate CIF (352×288) more than 30 frames per sec. These experimental results have met the purpose of system design. It means that the optimization methods are effective and the optimized system's decoding efficiency is 4-5 times faster than before.This paper realizes the MPEG-4 ASP video decoder system based on SOPC, and gets the average decoding rate CIF (352×288) less than 15 frames per sec. By optimizing the algorithm and hardware architecture of some modules in the decoding process, especially the YUV-RGB conversion module, IDCT and motion compensation module. By the hardware acceleration the optimized video decoding system's average decoding efficiency rate reached CIF (352×288) more than 30 frames per sec, which is basically consistent with the video decoding requirements of the applications on handheld terminal.