Modeling Of Network Processor Architecture And Design Of Prototype Chip

Network processor is one of core technologies which motivate the development of next generation network. Network processor must satisfy the requirements of processing capability and flexibility. Recently, the application of the network is extending continuously and various new network protocols are appearing, which requires network processor to keep up with these variety.It is one of the important challenges to adapt this requirement in the design of network processor architectures.This thesis aims to solve the problem that the network processor architecture faces and research the method of designing network processor. First, a method of modeling various network processor architectures is proposed in the earlier period design. Second, a network processor modeling framework is built to simplify the process of constructing architectural model. The model which is generated by this framework can be refined at different abstract levels and its performance can be evaluated easily. By this way, various NP architectural models can be optimized and compared with each other. Next, the essential factors and the key techniques for coprocessor design are discussed. By the comparison between serial mode and parallel mode of processor with coprocessor, asynchronous parallel mode is used to improve system performance. To increase utilization of coprocessor, Three shared mechanisms are evaluated i.e. Mutex Mechanism, Bus Arbiteror Mechanism and Coprocessor Pipeline Mechanism, to increase the system performance and reduce the cost of implementation.Finally, the prototype of network processor is developed using SoPC(System on Programmable Chip) technology in engineering process. The prototype contains four processing elements, which is able to forward IPv4 packets at the rate of 1Gbps.