The Design Of Image Realtime Processing System Based On SOPC

As the important means of information processing, Image processing technology has been widely applied in economy, culture and military fields. With the development of science and increasing of requirment, it is always desired to process and analyze large scale image information in time or in real-time, and how to improve image processing speed has already become a privotal problem in the image processing research field.At present the programmable embedded technology is a research hotspot in the electronic information domain in the world. The SOPC ideology based the programmable logic device is the key technology.It congregates parallel computation and parallel structure, and can fulfill the image processing tasks in real-time with the high speed.. In the paper,we bring forward a new scheme of image collection and processing by analyzing and comparing the features of various kinds of image collection and processing systems,in which,FPGA embedded Nios core is used as a center processor. The design method of the hardware circuit is described in detail. Therefore, it is very meaningful for SOPC to be applied to solve the problems in the real-time image/video processing and visual computation.This paper focuses on the three aspects below and achieves some results:1. The study on the hardware architecture design of the high-speed image processing systemBy analyzing the advantages and disadvantages of several methods of the high-speed image processing, it is concluded that it is superior to make image process using FPGA in working velocity and developing cycle. The system based on SOPC is brought forward,and the hardware design has been finished.2. The study on low-level image processing in SOPCOn the basis of analyzing the main ways of image processing and the resource of SOPC,some real-time low-level hardware image processing algorithm. Beside these,we compare and optimize the digital image filtering method,and implement fast median filter algorithm in FPGA; Making analysis for advantages and feasibility in use of the Sobel operator and system-level parallel pipeline processor to design circuits.3. Hardware platform structuresThe whole system circuit is designed, the off-the-shelf and custom components axe integrated into a SOPC system using the QuartusII software, the image sensor CCD and AD is controlled by VHDL programs.Whereafter,image datas are gathered from CCD,saved in SRAM and displayed in monitor.The filtering algorithm is designed in the NiosII IDE. At last the whole system is downloaded the FPGA on the Altera EP1C12Q240C8 developing platform to run and be test, the result of the experiment indicates the design of the image collection and processingsystem is correct.