Research On Secure Storage System Based On Chip Network Architecture

As the silicon technologies advance, the number of Intellectual Property (IP) cores that can be integrated onto one chip becomes larger and larger which leads to poor efficiency under traditional shared-bus architecture. Moreover, several distinctive challenges appearing along with the System on Chip (SoC) integration trend, as a result, on-chip packet-switched interconnection network is proposed as a solution to replace global on-chip wiring because of its capability to provide reliable, scalable, and efficient intercore communication. However, in contrast to its advantages,(Network on Chip) NoC also introduce new security challenges such as denial of service, extraction of secret information and hijacking. The potential weaknesses of NoC and corresponding countermeasures have not received deserved attention.This thesis focuses on research of security storage system based on Network-on-Chip with the goal to address security threats and guarantee the privacy and integrity of sensitive data. The advantage of this work is the security threat can be defended at a low hardware cost. To guarantee privacy and integrity of sensitive data, a coprocessor that can accelerate the Advanced Encryption Standard (AES) and SHA-3candidate Grastl algorithm is integrated into the RISC processor. The switching technique of the router support both packet-switch and circuit-switch to defend the bandwidth attack of denial of service. Network interface is a critical module between network and processing element or memory. To address the security problem of processing element accessing data of specific memory address space or memory-mapped peripheral device in NoC based system, a data protection controller is used to enforce access right control rules which specify what kind of authority a processing element has when initiating a transaction to access shared data memory. The algorithm of RSA is introduced for higher security requirement to guarantee only the processing element with the management right can configure the right access register.In order to verify the proposed scheme, the proposed coprocessor to support AES and Grostl algorithm is implemented into chip by the SMIC0.13um standard CMOS technology, and the proposed NoC platform is also verified through FPGA and synthesized using synopsys tool Design Compiler. The synthesis result shows that the hardware cost of network tile with32KB data cache,16KB private instruction memory and RISC processor with coprocessor is about525.2K equivalent NAND2gates. The hardware cost of the coprocessor is about3.9%while the secure network interface is about1.1%of the network tile. The hardware cost to defend security aspect of NoC domain is small. The throughput of AES-128and Grostl-256is365Mpbs and205.3Mbps respectively. The coprocessor and the secure network interface achieve the target of performance and can be applied to system based on NoC architecture.