Research Of Reconfigurable Cycle Accurate Simulation Platform For Embedded Processor

In the last decades, instruction set simulator has became an essential development tool for the design of embedded processor. It is a simulation platform that builds on the existing computer system for an under developing processor. Designers can execute programs on these models to validate the performance and correctness of a proposed hardware design. Programmers can use this software models to develop and test software before the real hardware becomes available.This thesis studied the design methods of instruction set simulator, and the implementation of hardware-software co-simulation. We develop a software simulation platform with C/C++. This platform contains a reconfigurable cycle accurate instruction set simulator, whose target processor is CK510, an embedded processor developed by Zhejiang University. It also contains a bus function model of AMBA AHB, and a Procedure Language Interface (PLI) developed with VPI library. Our instruction set simulator is an interpretive simulator, which implements with execution driven approach. In order to get accurate simulation result, it models the pipeline architecture and exception handle of CK510 completely.The cycle-accurate simulation flat is reconfigurable. Foremost, the instrunction set simulator is reconfigurable, users can modify the cache size, associative way number, the size of branch history table, the big endian or little endian. Secondly, the environment of simulation is reconfigurable. It has a stand-alone mode with an external environment simulatied in C++. It also can simulate in Verilog mode, the C++ external environment is disabled and simulated with Verilog.