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The Design And Implementation Of An Interpretive Instruction Set Full System Simulator

Posted on:2013-09-16Degree:MasterType:Thesis
Country:ChinaCandidate:J XiaoFull Text:PDF
GTID:2248330392957872Subject:Computer application technology
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Along with widely application of embedded system, more and more functions areintegrated into these systems. What’s worse, the evolution period of these systems is alsobecoming shorter and shorter. And all of these cause the huge stress for the people whoare responsible to the design and development of embedded systems. Parallel of designand development of hardware and that of software is a must requirement, which havepushed a rapid improvement of the instruction set simulation which is also extensivelyused in the design and verification of new micro-architecture domain. So it is theoreticaland practical meaningful to do research to provide a fast interpretive instruction set fullsystem simulator.According to the advantage of flexibility and accurately and disadvantage of theinterpretive instruction set simulator, a simulator IISimulator based on interpretiveinstruction set simulation technique which is based on shared basic block cache technique,which sufficiently exploits the temporal and spatial locality of the execution ofapplications, is designed and also implemented. The shared basic block technique cachesthe decoded results of target machine instructions in basic block, when the next time thebasic block is going to be executed again the decoded results are directly used, whicheliminates the time-consuming fetch-decode phase appearing in the interpretive instructionset simulator. And shared memory pool is also introduced to reduce the overhead ofmemory management coming along with caching.During the experiments phase of IISimulator, we chose some representative testexperiment applications of the target machine for testing. With the statistic data ofsimulation speed of IISimulator running these tests under non-cache, instruction-cache andbasic-block-cache circumstances, we came to the conclusion of the superior of basic blockcache when compared to the other two. Experiments used to verify that the sharedmemory pool may improve the simulation speed of IISimulator were also taken out, andthe result shown it does. When compared the average simulation speed to other full systemsimulators such as skyeye and SimpleScalar, IISimulator win. All these experiment resultsindicated that the improvement that we made to interpretive instruction set simulationtechnique gives big payoff.
Keywords/Search Tags:Interpretive instruction set simulator, basic block cache technique, sharedmemory pool, full system simulation
PDF Full Text Request
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