Design Of ARMv4 Instruction Set Simulation Platform

Today, designers of next-generation embedded processors and software are increasingly faced with short product lifetimes. The resulting time-to-market constrains are contradicting the continually growing processor complexity. In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance is a key factor for the overall design efficiency. Motivated by the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. However, due to the restrictiveness of the compiled technique, it has not been able to push through in commercial products. In this paper, a simulation platform for ARMv4 instruction set is developed, which includes a simulation engine that combine the benefits of both compiled and interpretive simulation.First, we introduce the programming model of the ARMv4 instruction set, including the processor modes supported, the register organization, the memory organization and the exception behaviors.Then the simulation platform is built, in which part we design the simulation engine that combines the performance of compiled simulators with the flexibility of interpretive simulators; accomplish the description of the ARMv4 instruction set; implement the memory interface that meets the request of the objective instruction set to access memory; introduce the format of the ELF files and design a load program to load the instruction words and data words in the ELF files into memory.Finally, the functions and the performance of the simulation platform are verified. In the functional verification, instruction functions and exception behaviors are verified. In the performance verification, ADPCM program and GSM program are used as benchmarks to indicate the performance improvement achieved by using our simulation engine.