Implementation Of RSA Crypto Chip Based On FPGA

With the development of society information, network technology is applied extensively. At the same time the opening of network bring much hidden trouble of secutity to information., cryptography is the key technology.RSA is mature public-key cryptography at present, it can encrypt , make a scratch of digital and validate degree. RSA is applied in many secure system. The large number exponentiation algorithms is the key of RSA Cryptography System, which is performed by a series of modular multiplication. Exponentiation algorithms and modular multiplication are bottlenecks of efficiency. Their efficiency decides the efficiency of RSA.In order to improve the speed of RSA, this paper study RSA cryptogram arithmetic in depth, bring forward a parallel arithmetic, which combined secret key from right to left scan mode and FIPS operation mode of Montgomery arithmetic, which shift the operation efficiency of RSA arithmetic. And, give the total design scheme and system structure of RSA cryptogram chip, expound the design technology and method of high speed parallel RSA arithmetic hardware using three steps pipeline technology. Discuss the method and process of implement the RSA cryptogram chip based on Altera' s FPGA, and analyze emulate validate result of software and hardware implement.In the course of implementation, multiplexing and shared technology are utilized. The resource of chip is saved effectively. Using pipeline technology to improve efficiency and speed. The final implementation of 1024-bit RSA chip is based on Altera EP1C12Q240C6 of Cyclone. The chip is validated by software and hardware.