Fast Implement Of Modular Exponentiation And Modular Multiplication Of RSA Algorithm Based On FPGA

Security is becoming increasingly important features with the expansion of internet services like electronic commerce.Public key cryptography is an important solution for sequirements. Security of RSA algorithm is based on large integer factorization of the difficulty of the problem of large integer factorization problem is the mathematical term, there has been no effective way to be resolved, the RSA algorithm is by far higher degree of recognized security algorithm.RSA algorithm is the most widely used public key algorithm among all the Public key cryptography algorithm.In terms of data encryption processing in RSA algorithm,the fundanmental operation is to compute modular exponentiation by repeated modular multiplication. Montgomery algorithm is a great contibution on solving this problem.RSA cipher algorithm requires a large operation mode refers to the number of operations, the currently accepted model of length 512-2048bit, computing strength is very large, with the software approach will be very slow, so we use for FPGA implementation of Montgomery algorithm RSA algorithm. Because RSA encryption system operation involved a large integer multiplication and addition, so processing speed is slower. How to improve the speed of high-precision multiplication and division operation is a key issue, and RSA's FPGA implementation of speed and security have unparalleled advantages.In this paper,new RSA structures are presented.They are built around a modified version of Montgomery's multiplication algorithm. Because RSA encryption system operation involved large integer multiplication and addition, so processing speed is slower. How to improve the speed of high-precision multiplication and division operation is a key issue, and RSA's FPGA implementation of speed and security have unparalleled advantages. This RSA cipher algorithm implemented new hardware structure of the Montgomery modular multiplication algorithm is improved, the fast recursive algorithm for big integer multiplication of Karatsuba Montgomery modular multiplication algorithm is applied to a form-FIPS algorithm. Achieved compared to previous structures, the improved algorithm can reduce the hardware resources and also enhance the computing speed.This article based Modular multiplication and hardware requirements of the modular power system analysis and design, increased computing power power RSA modulus. Expounds the RSA cryptographic chip design and implementation process, the system partition on the basis of the module, through the process of the algorithm, the algorithms in the analysis of timing, the use of calculators and the encoder combination to achieve a model power, mode by two controllers. Discussed in the Xilinx FPGA on the implementation method and process, and with the Verilog language code implemented in the ISE and Modsim environment for the conduct of the simulation.