Power Model And Power Optimization Based On Reconfigurable NoC

With the development of integrated circuit, the power of NoC becomes the restraining factors. Limited by the chip area and bandwidth, the power optimization of NoC has special requisition. The work of thesis is to design a reconfigurable NoC on RTL level, create the macro power model, optimize the power, and design the NoC system based on application.A reconfigurable NoC is designd in the thesis,used for power model and power optimization. The reconfigurable parameters includes the topology, virtual channel number, buffer depth, and flit width. A new router structure with separate data channel and control channel is improved in the NoC design. Then a macro NoC power model is created based on the parameter of virtual channel number, buffer depth, and flit width.The power model coefficient and accuracy is fixed by the synopsys EDA software. Because of the influence of vitual channel power, a vitual channel allocation optimization algorithm based on Simulated Annealing is proposed to reduce the NoC power by increasing the utilization ratio and reducing the total number of vitual channel. The optimization result is evaluated by the reconfigurable NoC.Finally, the thesis researches the division and mapping of application task based on the H.264 decoder, designes the compatible NoC, optimizes the NoC power by allocating the vitual channel, and completes the back-end design of whole system.