NoC Router And Low Power Communication Network Design

With the advent of chip multi-processors (CMPs), traditional SoC based on bushas become increasingly unable to meet the demand of systems, such as communica-tion bandwidth and scalability, etc. Network-on-chip (Noc) is an appealing alternativefor communication in SoCs with capability of providing high throughput, low latencyand scalability. The performance of NoCs depends heavily on the on-chipcommunication fabric whose core component is router.Based on the discussion of the key technologies of NoCs, a virtual channel routeris designed. The router is based on2D-Mesh topology, using the GALS clock strategy,XY dimension order routing algorithm, the wormhole flow control mechanism and lowlevel flow control based on credit. This paper introduces the router modules in detail,including the input channel, the input controller, the routing computation, the virtualchannel allocator, the switch allocator, the credit allocator, switch, etc. This routercomprises5bidirectional ports, each port comprises4virtual channels. The adoptionof virtual channels improves the performance of the on-chip communication fabric.The function simulation verifies the correctness of the router, gatelevel netlist isgenerated by synthesis.The power of the communication network becomes a major concern in therouter-based NoCs, it is critical that the network provides low power communicationsthat scale to high core counts. The low power technologies related to router andcommunication network are diccussed, and then low-swing signaling, serial encodingand low power FIFO are used to reduce the power consumption of the network. On theinput of square wave signal, compared with full-swing interconnection with repeatersinserted, the power consumption of low-swing interconnection decreases by31.69%.Compared with FIFO without gated clock, the area of low power FIFO with gatedclock increases by6.1%, but the power consumption is reduced by25.7%.