The Research Of Network-on-Chip Router With Dynamic Virtual Channel Regulator

As a new system architecture for IC chip design, network-on-chip(NoC) has solved the problem of poor extension、being difficult to manage the clock、being limited for address space et al in system-on-chip (SoC) through drawing on the idea of computer network. NoC is likely to replace the SoC, to be the main solution for IC design in the near future. NoC router is the core component of the system, directly determine the performance of the interconnection networks. In this paper, I regard the dynamic virtual channel allocation for NoC router as a research target, and do a detailed analysis and exploration for that type of router architecture and blocks. In order to solve the problem of communication lines too long for these routers and other multi-channel distribution arbitration latency, a low-latency network router architecture with dynamic virtual channel regulator is proposed.The designer set the two low latency policies into the NoC router with dynamic virtual channel allocation, and then there is a mixed low latency router formed. This paper mainly from three aspects realizes of the router’s low latency requirements. Firstly, the parallel execution of SA and VA is realized by using Speculation architecture, which reduces the nodes in the data packet processing delay. This process, which acts on flits, has been completed only for VC allocation in the fast distribution module flits. Secondly, we take advantage of rapid distribution module, which bring about the logic operation by using a fast allocation request signal from the next clock cycle to generate the output port and VC distribution control signal quickly, to achieve the VA and SA parallel more easily. At last, some flits would be calculated by look ahead router mechanism at previous router, and then, routing the bypass flits with computational results and generic flit to the current router, the bypass flits will be buffered in the input channel without calculation, this process contribute to reduce the calculation pressure of the first stage in the routing pipeline and reduces network latency between nodes forwarding.By BookSim2.0 simulation platform, network throughput and latency both for mixing low-latency router architecture was proposed performance evaluation. And at the same topology, routing algorithm, the initial virtual channel number and other conditions, compared the performance results with the low latency policy of Speculation and Lookahead. The simulation results show, mixing low-latency routing architecture proposed in the throughput and low-latency are better than the other two strategies, which proved the feasibility and correctness of the architectural design.