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Research On A Chip-MultiProcessor Architecture And The Way Of Developing Test Vector

Posted on:2005-03-28Degree:MasterType:Thesis
Country:ChinaCandidate:K B WangFull Text:PDF
GTID:2168360152468074Subject:Computer Science and Technology
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In the past twenty years, there were main two factors that have been fueling the microprocessor performance growth: the great advancement of semiconductor technology and the development of microprocessor architecture. With the great advancement of semiconductor technology and the increase of integration density, the research on system architecture has met a new problem how to use more and more transistors on a chip. CMP(Chip Multiprocessor) is proposed in late 1990's, which is an effective way of using the transistors and improving the system performance. Nowadays, researchers on the microprocessor architecture field show great interest in CMP.The tsinghua university project of embedded microprocessor design is a major national 863 program; CMP is its extended project. The research team has successfully developed the "Thump107" processor with MIPS32 architecture, which is high performance, low power consumption embedded processors with our own intellectual property right. The characteristics of the processor make it suitable for the core of CMP. Our CMP system is named Thump107-CMP. Thump107-CMP is composed of two processors, which are coordinate and implement the coarse parallelism. Because of being able to use the Thump107, The key part of the project is the CACHE coherence protocol based on the snoopy WISHBONE bus on chip. The protocol is control simple and scalability. The WISHBONE bus is suitable for system communication on chip and configurable. The bus on chip effectively solutes the IP migration and design reuse. Firstly, the article starts with the present research on CMP, including several successful CMP systems and summarizing the functional and architectural characteristic of CMP system. Secondly, the article introduces the CMP system design specification, including core, CACHE, bus on chip, and communication between cores specification. Lastly, the article discussed the way of generating the effective test vector aiming to reaching excellent functional cover.Through designing and implementing THUMP107-CMP, the ideas and methods which are demonstrated in this paper are practiced and verified. Valuable experiences for designing CMP are accumulated in this process, which can be beneficial references for the future researchers.
Keywords/Search Tags:CMP, CACHE coherence, SOC, test vector
PDF Full Text Request
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