Analysis And Implementation Of Cache Coherence Protocols For CMP

Advances in IC processing allow for more microprocessor design options. The increasing gate density and cost of wires in advanced integrated circuit technologies require that we look for new ways to use their capabilities effectively. So comes CMP.In a chip multiprocessor system, multiple CPUs may simultaneously read and write the same memory locations. A memory model for a shared-memory system is an architectural specification of how memory operations of a program will appear to execute to the programmer. The memory model affects the ease of programming and the performance of the system as well. In a chip multiprocessor system, each CPU core has its own cache. Cache coherence is a prerequisite for achieving correct memory behavior in systems that allow the caching of shared data. It is an important part of the overall scheme for supporting a memory model. To enable higher performance, current cache coherence protocols allow transactions to be split and allow multiple outstanding requests. This complicates the implementation of coherence protocol by introducing transient states, so as the specification of the protocol.In this project, we address the constraints to the implementation of cache coherence imposed by a memory model. A scheme which satisfies a sequentially consistency memory model is given for snooping protocols. The implementations of MSI and MESI are introduced and a "non-full division" to partition the read miss in the case that message is not served by all CPUs simultaneously is proposed and proved to be feasible. A cache simulator written in c langue is prepared, and some DSP programs were executed to estimate the implementation of the protocol. Based on the analysis of the statistics obtained through the runs of the programs, some directions or instructions which may optimize the design of CMP system are given.