Block-aware instruction set architecture

This dissertation examines the use of a block-aware instruction set architecture (BLISS) to address the front-end challenges of modern processors. The theme of BLISS is to allow software to assist the front-end hardware by providing architecture support for control-flow prediction and instruction delivery. BLISS defines basic block descriptors in addition to and separately from the actual instructions in each program. A descriptor describes the type of the control-flow operation that terminates the block, its potential target, and the number of instructions in the basic block. This information is sufficient for fast and accurate control-flow prediction without accessing or parsing the instruction stream. The architecture also provides a flexible mechanism for communicating compiler-generated hints at basic block granularity.; The BLISS ISA suggests a decoupled front-end organization that fetches the descriptors and the associated instructions in a decoupled manner. The front-end uses the information available in descriptors to improve control-flow accuracy, implement guided instruction prefetching, and reduce the energy used for control-flow prediction and instruction delivery. We demonstrate that the new architecture improves upon conventional superscalar designs by 20% in performance and 16% in energy. We also show that it outperforms hardware-only approach for decoupled front-ends by 13% and 7% for performance and energy respectively. These benefits are robust across a wide range of architectural parameters.; We also evaluate the use of BLISS for embedded processor designs. We develop a set of code size optimizations that utilize the ISA mechanism to provide code size reduction of 40% while maintaining a 10% performance and 21% energy advantages. We also develop and evaluate a set of hardware and software techniques for low cost front-ends for embedded systems. The optimization techniques target the size and power consumption of instruction caches and predictor tables. We show that the decoupling features of BLISS and the ability to provide software hints allow for embedded designs that use minimally sized, power efficient caching and predictor structures, without sacrificing performance.