| The reconfigurable cryptographic instruction set processor,which adopts reconfigurable cryptographic operation functional unit and specific instruction set,is designed to implement various cryptographic algorithm,and it holds the efficiency and flexibility both in the procedure of processing.However,the architecture and instruction set vary in different reconfigurable cryptographic instruction set processors,which brings programming and compilation optimization problems to applying cryptographic in processors.In this thesis,the following researches have been carried out for solving the mentioned problems:1.The DSLBCA(Domain Specific Language for Block Cipher Algorithm)is studied.General programming language is difficult to describe the operator and structure of block cipher algorithm intuitively.To solve this problem,the method of domain-specific language modeling is used to establish a block cipher algorithm encryption process feature model,hierarchical feature model and execution model from the perspective of problem domain and answer domain.The data type,identifier,function structure and program control structure of the DSLBCA language are defined;with the help of DSLBCA's abstract expression ability of block cipher operators,users can write block cipher algorithm program code through mathematical thinking;2.The compiler infrastructure for DSLBCA and RVBCP(Reconfigurable VLIW Block Cipher Processor)is studied.The block cipher description language in the existing research cannot be compiled and executed in the reconfigurable cipher processor.For this problem,the domain-specific language automation development tool ANTLR(Another Tool)is used to design the corresponding compiler infrastructure,according to the instruction set characteristics of the RVBCP and the language rules of the DSLBCA,which realized the symbolic compilation of the DSLBCA program code to the RVBCP assembly instruction set;3.The compilation process of DSLBCA program code under heterogeneous So C(Syetem on Chip)is studied.According to the workflow of the heterogeneous So C based on the RVBCP multi-engine architecture and the source code characteristics of the DSLBCA application,a feedback compiler structure and an unrolling factor algorithm UFACLA(Unrolling Factor Based on Average Code Line Amount)are proposed,the parallel distribution of the DSLBCA source code under the So C is implemented in the front end of the compiler;the scalar replacement of the unrolled codes is performed,which improves execution efficiency of the block cipher algorithm by reducing the memory access time;4.The operators automatic mapping of the DSLBCA program code in RVBCP is studied.The block cipher operator scheduling parameter model is established to quantify the scheduling status information of operator nodes,and the RVBCP computing resource and register resource parameter model is established to quantify the consumption of computing resources and register resources at runtime.Thus,a parallel resource allocation algorithm for multi-transmission reconfigurable block cipher algorithm instruction set processor is designed,based on greedy strategy,list scheduling and Based on the idea of linear scanning algorithm.Consequently,the automatic parallel mapping of block cipher operators on RVBCP is realized.5.The low-power instruction scheduling of the compilation back-end is studied.The relationship between VLIW(Very Long Instruction Word)instruction level power consumption model,RVBCP's instruction word internal ordering and dynamic power consumption changes are analyzed,then the scheme of adjusting the entire Hamming distance between instruction words,and the low power are mathematically described and discussed.The instruction power consumption scheduling problem can be summarized as a generalized traveling salesman problem.And an improved generalized genetic algorithm based on tabu search is proposed to solve the generalized traveling salesman problem,which realize low-power instruction scheduling for RVBCP. |
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