Parallel Co-processor Architecture Research And Instrcution System Design For Block Ciphers

Traditionally, cryptography can be implemented with two methods; one is in processor routine, the other is directly in hardware, such as ASIC. Both of them have vital advantage and disadvantage. The problem of processor is low executive performance, but it has sufficient flexibility. As to ASIC design, the operation speed can achieve wonderfully high level, but aiming at one or few algorithms make it lacks of prevalent adaptability. Aiming at the above contradiction, this thesis had a research on the efficient and flexible crypto architecture for block cipher algorithms.Based on analyzing the operation character of block ciphers, we set forth a solution for efficient cryptographic processing, and put forward a parallel co-processor architecture for block ciphers, which supports word and sub-word parallel processing, and its micro realization is schemed out too. The design gives attention to two aspects which is flexibility and high performance, including consummate control capability, efficient operation capability, and reconfigurable cipher process capability.For improving the parallelizability of the co-processor, a set of new efficient instruction is introduced, including S-boxes substitution, general bit permutations, arbitrary rotates, modular arithmetic and so on. These instructions have developed parallelizability of inner single instruction and multi-instructions to advance performance.A convenient verification platform is also studied in this thesis. It is implemented in FPGA hardware platform and achieves unit and system verification.Finally, in synthesis, the design is fabricated on 0.18um CMOS cells through Design Compiler tool, and the performance of this co-processor is compared to other hardware/software implementation.In conclusion, this co-processor has high performance of instruction implement, high instruction level parallelism, and broad applicability. It can flexibly and effectively realize block ciphers, and it is a new architecture of block cipher process.