Hybrid Register File Architecture Research For Reconfigurable Block Cipher Processor

Compared with specific circuit ASIC and custom instruction set processor ASIP, coarse-grained reconfigurable processor performs better in the key indicators of performance and flexibility for the need of cryptographic algorithms dynamic reconfiguration in specific domain. It has become an important research direction in related fields. Especially, the bandwidth limitations, memory access delays and mapping methods of the register file are the bottlenecks when block cipher algorithm implemented by reconfigurable design method. In order to meet the demand for performance and area of block cipher algorithm, the present study focused on the high area efficiency (performance area ratio) of block cipher reconfigurable processor register file.From the block cipher algorithm characteristics, this study statistically analyzed the impact of algorithms and data flow characteristics, which provided theoretical support for architecture optimization of block cipher reconfigurable processor. A performance analytical model of the block cipher reconfigurable processor was established by abstracting cipher circulation core, architecture resources and mapping methods. And this model optimized the design of global register file and local register file. Based on the research of the hybrid register file, a reconfigurable cryptographic processor for block cipher algorithm was implemented. The specific research and innovations are as follows:Firstly, for the performance bottlenecks of block cipher reconfigurable processor caused by the global register resource constraints, a global register performance model depended on the architecture and algorithm characteristics was proposed by analyzing the number of round function of block cipher algorithm, reconfigurable rows and the configuration dwell time in reconstruction process. This model could be used to optimize the design parameters of the global register file. The experimental results showed that the algorithm performance of the global register file optimized by the performance model increased by 17.24% on average than similar work under the same constraints of algorithms set and architectures feature.Secondly, to resolve the problem of area resource overhead of global register file caused by the large storage capacity and connectivity range, a grouping whole interconnected distributed global register file structure which was based on the reduction register interconnection-wide policy was proposed by analyzing features that the block cipher function doesn't interact with each other on the wheel data and the data dependent on the read-after-write inner wheel data. The experimental results showed that compared with similar studies, the area resource overhead of the register file reduced 41.92% with the same parallel data access capability.Thirdly, to meet the complex needs of content variability and structure diversity of S-box in block cipher, a cross-domain register file with diversified block ciphers and multi-ported and unified structures was proposed, which effectively reduced the area resource overhead of local register file. This was accomplished through two steps:ascertained the constraints of input and output data width, number and size of S-box in the manner of analyzing the algorithm, and then extracted the minimum capacity of the local register file and minimal access concurrency which could satisfy the target cryptographic algorithm set. The experimental results showed that compared with the similar studies, the area overhead of local register file structure based on the maximum degree of algorithm parallelism reduced 26.14%.The above findings from hybrid register file have been applied to a block cipher reconfigurable processor studied by our group. They have been taped out already. Compared with other register files, the area efficiency of hybrid register file in this study improved 117.21% on average by selecting the 14 mainstream block cipher algorithm as the experimental test collection. Compared with other register file architectures of reconfigurable cryptographic processor, area efficiency of the hybrid register file architecture increased 66.56% on average. The results of physical design showed that area efficiency of block cipher algorithm of reconfigurable cryptographic processor improved 10.62%?40.48% than other cryptographic processors.