The Research And Implementation Of Key Techniques On Block Cipher ASIP

Application Specific Instruction-Set Processor (ASIP) for cipher processing can achieve a compromise between flexibility and performance, by instruction-set and architecture design based on characteristics of cipher processing. Therefore, ASIP becomes the research hotspot of cipher application. The difficulty is to improve performance more, which is based on high flexibility. To solve this problem, this paper has researched and implemented key techniques of Block Cipher ASIP, according to processing characteristics of block cipher.This paper has studied clustered design technique. According to static processing characteristics of block cipher, clustered architecture with word and hyper-word modes is presented. The design of this architecture has not only efficiently reduced critical path-delay, but also improved the flexibility of processing different algorithms.This paper has studied exploiting techniques of Operation Level Parallelism (OLP), Instruction Level Parallelism and Thread Level Parallelism. According to dynamic processing characteristics of block cipher, the OLP exploitation of word cluster is presented, the pipeline structure is designed, and the Unsymmetrical Multiple Thread Mode is presented. By systematical exploitation of three levels parallelism, the performance of Block Cipher ASIP is improved.Block Cipher ASIP is implemented and validated on FPGA. Finally, Block Cipher ASIP is fabricated on 0.18um CMOS cells. Experiment results indicate that Block Cipher ASIP not only has the flexibility of processing familiar block cipher and hash algorithms, but also has high performance.