Design And Optimization Of A Coarse-grained Reconfigurable Architecture For Stream Cipher Algorithm

The reconfigurable cryptographic processor combines the flexibility of a general purpose microprocessor and the efficiency of a special cryptographic chip.It has achieved a good balance between the two key indexes for the flexibility and efficiency of calculation.Stream cipher algorithm plays an important role in cryptosystem.In this thesis the structure and operation characteristics of the cipher algorithm are analyzed,and a kind of coarse-grained reconfigurable cryptographic processor which can efficiently implement multiple stream cipher algorithms is designed,which mainly research contents are as follows: On the one hand,regard to the the variable structure characteristics of the feedback shift register in different stream cipher algorithms,this thesis counts multiple parameters and presents a reconfigurable feedback shift register structure that can feedback series,number,tap position and tap number of a feedback shift register.The reconfigurable feedback shift register structure is used to realize the implementation of multiple stream cipher algorithms in the same hardware structure.On the other hand,based on the basic operation types and data characteristics analysis of nonlinear function of multiple stream cipher algorithms,the reconfigurable functional units that support single cycle and multi operation computing are customized.Regard to the performance bottleneck caused by the data dependence of the feedback shift register in the nonlinear function of the stream cipher algorithm,a reconfigurable array structure which can implement the forward extraction and pipelining operation is designed in this thesis,with improving the implementation performance of stream cipher algorithm.In this thesis,the prototype of the stream cipher reconfigurable processor is implemented and verified on the FPGA platform.Three algorithms,Trivium,ZUC and SNOW3 G,are mapped on it.The experimental results show that the performance of the corresponding algorithm is 1.31Gbp/s,2.18Gbp/s,and 3.26Gbp/s respectively.Compared to traditional singlebit serial implementations,the Trivium algorithm generates a 32-bit key each time in the multibit parallel structure proposed in this thesis,and the normalized performance of Trivium can be increased up to 5.3 times.Compared with the existing reconfigurable processor,the normalization performance of ZUC and SNOW3 G can be increased by more than 4 times.