Design And Optimization Of Energy-efficient Coarse Grained Reconfigurable Architecture For Block Cipher Algorithm

Coarse Grained Reconfigurable Architecture has the advantage of high efficiency and flexibility as a noval reconfigurable computing processor,which can implement a variety of block cipher algorithms with fewer resources.In recent years,computing resources of reconfigurable processor are increasingly rich,and the area of the array is increasing,which limits the performance due to overhead of configuraton.In addition,the operation of S-box and subkey-reading in block ciper algorithm leads to large amounts of power consumption by data access,so the energy-efficiency of the processor is limited.Therefore,it plays a very important role to establish a set of effective configuration management strategy and computational resource management scheme to improve the energy-efficiency of reconfigurable system.This thesis proposed the dynamic reconfiguration and partial reconfiguration considering the algorithm configuration strategy——the hierarchical context organization scheme.The proposal not only hided the switch time of configuration context,but also optimized the context transmission time for data flow diagram.In the configuration scheduling,the proposal dramatically compressed the idle time between the data streams that were configured to switch the process through the proposed configuration package pre-resolution scheme,minimizing the configuration context switching time,thus improving the reconfigurable efficiency of the reconfigurable system.In addition,this thesis also proposed energy-efficient data management program for block cipher algorithm.We proposed a sharing strategy and a clocking gating strategy for S-box module.Sharing could reduce the overhead of S-box resources while clock gating could eliminate switching power of S-box resources.We also proposed a data separation strategy for General purpose register file.The subkeys were stored in a register file because of concurrency access while the intermediate results were stored in memory.The purposal above was to reduce the switching of the memory module,thus reducing power consumption.The circuit was realized finally under TSMC 65 nm CMOS technology,with the area of 4.12mm2 and frequency of 500 MHz.The architecture was suitable for most of the SP network structure and Feistel network structure of the block cipher algorithm.The energy-efficiency of AES and DES achieved 69.7Gbps/W and 18.1Gbps/W,which was superior to the design target.The energy effiency ratio increased by more than 40%compared to the original design,and the implementation has increased by 117%-480%compared with the implementation of the same existing platform.