Design Of DPA-Resistent Scheme For Coarse Grained Reconfigurable Architecture

The crypto chip plays an indispensable role in information security,with demand for high performance,low resource overhead,low power consumption,and high-level security.The General Purpose Processor(GPP)can be used to implement various cryptographic algorithms which can be accelerated by dedicated instruction or parallel technology,but it is difficult to meet the practical requirements in terms of area efficiency and energy efficiency.Algorithms implemented in Application Specific Integrated Circuit(ASIC)obviously have advantages in terms of performance,area efficiency and energy efficiency,but have poor flexibility,since ASIC is only limited at some specific algorithms.On the hand of security,both GPP and ASIC implementations would pay a great cost of performance and hardware overhead to resist the power attack.In this thesis,a Coarse Grained Reconfigurable Architecture(CGRA)is proposed for the block cipher algorithms,which can achieve a good compromise between performance and implementation efficiency,and can significantly reduce performance overhead and hardware resource cost while effectively resisting Differential Power Analysis(DPA)attack.In this thesis,different security protection schemes are adopted for the linear operations and the nonlinear operations in cryptographic algorithms.For the linear operations,the Register Secret Share Scheme was designed based on Boolean mask,so that the linear part can resist the first-order power attack.The Register Secret Share Scheme was implemented using idle resources in CGRA to reduce the growth of area overhead,and the problem of performance overhead caused by idle resources configuration was alleviated by partial reconfiguration.For the nonlinear operations,the Dynamic Reconfiguration Scheme of Data Path was designed.Using time margin in the data path before and after the implementation of S-box opration to construct data paths with different delays,would not affect the highest frequency of the architecture,and greatly improved the capability of anti-attack.The CGRA of anti-power attack was implemented based on the platform of SAKURA-G FPGA development board.The Hamming Distance and Hamming Weight power model were used to verify the capability of anti-attack.The experimental results show that the anti-attack capability of the DES and AES algorithm are both more than 2,000,000 power traces with the hardware resource cost only increased by 10.4%and the performance cost only decreased by 2.1%and 2.5%respectively.