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A Traffic Model For Chip Multiprocessor Interconnection Network Memory Access Behavior

Posted on:2019-02-11Degree:MasterType:Thesis
Country:ChinaCandidate:C C SunFull Text:PDF
GTID:2428330590475449Subject:Software engineering
Abstract/Summary:PDF Full Text Request
Networks-on-chip(NoC)traffic is the basis for evaluating network performance,and its traffic model can fully capture the traffic behavior that emerges on itself.In the initial stage of chip architecture design,the traffic model can be used as a load input to make preliminary and rapid evaluations of the NoC and system-on-chip,therefore,the quality of the NoC traffic model is directly influence the success of the systemon-chip modeling.At present,the existing NoC traffic models include short correlation model and self-similar model.However,both of them have not focused on the impact of read and write behaviors emerging in the on-chip network,and they can not accurately assess the performance of the shared cache NoC.In this dissertation,for a multi-core system with shared cache CMP architecture,We studied the influence of read and write behaviors on NoC traffic distribution,and a traffic model suitable for shared cache network architecture evaluation is proposed.The detailed contents are listed as follows:(1)The different traffic characteristics of the read and write behaviors in the NoC were analyzed through experiments.Based on the traffic characteristics of the read-write behavior,relevant feature parameters were extracted to form a traffic model with three parameters.(2)A simulation platform was built to extract traffic data from NoC,and the data were quantified based on the extracted feature parameters.Moreover,a synthetic traffic tool was designed to fit the characteristic parameters obtained by the model into traffic data which can be injected into the NoC simulator.(3)The Husrt parameter value,accuracy and operating efficiency of the traffic model were verified.The experimental results show that the precision error of the traffic model proposed in this dissertation is less than 5%,and this traffic model can save 70% time in comparison with the full simulation.Compared with the traffic model without the memory access behavior,the accuracy of the traffic model proposed in this dissertation is enhanced by 10%.Moreover,it is verified that this traffic model can be applied to other topology structures of mesh and turos.
Keywords/Search Tags:Heterogeneous Multi-core, NoC, Traffic Model, Memory Access
PDF Full Text Request
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