Research On Dynamic Binary Translation Based Co-designed Virtual Machine

Microprocessor industry is promoted by the rapid development of very large scale integration technology and the increasing magnitude of application requirements. There are new challenges and opportunities for the architecture design of microprocessors. Architecture innovations, which enable efficient system designs to achieve higher reliability, lower power consumption with lower complexity and cost, are required. But after decades of development, a huge amount of applications/software have been accumulated for legacy instruction set architectures. Binary compatibility for the legacy architecture has inhibited modern processor designers from developing new architectures and limited the use of the innovation techniques. Co-designed Virtual Machine (Co-VM) technique combining software and hardware enables a different approach to microprocessor design, where the host architecture is designed concurrently with the VM software that runs on it. Co-VMs decouple the software architecture and the hardware architecture. Thus, Co-VMs can not only release the processor designers from the burden of ensuring cross-platform compatibility but also provide new opportunities for innovation.This dissertation focuses on the design and implementation of Co-VMs. We discuss several key issues, such as the model and infrastructure of a Co-VM, the performance of a Co-VM, the approaches to reducing the startup overhead and steady execution overhead of a Co-VM. A Co-VM prototype is also implemented, which demonstrates the correctness of our Co-VM model and the effectiveness of the dedicated optimization approaches proposed in this dissertation.The main contributions are as follows:1. We propose a Dynamic Binary Translation based Co-VM Model (DBTCVM). This model targets on compatibility and high performance. DBTCVM uses a two-staged dynamic binary translation strategy that interpretation is used at the initial stage while translation performs on hot code. Dedicated hardware supports are used for source architecture mapping in DBTCVM. Based on the principle of Turing machine, this dissertation also proposes a formal definition for DBTCVM, which provides a theoretical basis for this dissertation.2. We propose a Decoded Instruction Cache (DICache) for reducing the startup overhead of a Co-VM. Startup performance is critical for a Co-VM. We first make a deep analysis and evaluation on the startup overhead of a Co-VM and observe that interpretation is the main resource of the startup overhead. We observe the locality of the interpreter routines and propose a DICache infrastructure for saving intermediate results produced during interpretation. With DICache, most redundant instruction decoding operations can be avoided. Experimental results show that DICache can dramatically reduce the interpretation overhead at a low hardware implementation cost.3. We propose a DICache-based Hybrid Threaded Interpretation Strategy (DHTIS). The organization strategy of an interpreter has an important impact on its performance. Centralized interpretation is inefficient while the traditional threaded interpretation is not suitable for interpreting the CISC ISA because of the complicated instruction decoding process. DICache can dynamically predecode the source instruction and convert them into an intermediate form. DHTIS appends the simple DICache access code at the end of each interpreter routine, thus enable the threaded interpretation for CISC ISA. DHTIS can further reduce the startup overhead of a Co-VM.4. We propose a Direct Control Transfer Chaining (DCTC) technique for reducing the steady execution overhead of a Co-VM. The translated code is stored in the code cache of a Co-VM as superblocks. Conventional code caching systems suffer from overheads when control is transferred from one cached superblock to another. This also has a great impact on the steady execution performance of a Co-VM. The DCTC technique chains the direct control transfer instructions by set their target addresses with the translated target addresses. Experimental results show that DCTC can effectively avoid most table lookup and contex switch operations, which reduces the steady execution overhead of a Co-VM.5. We propose a dynamic chaining technique for indirect control transfer instructions based on Indirect Transfer Target Buffer (ITTB). The indirect control transfer instructions have their target addresses stored in a register or memory, and the register value or memory value can change over the program's execution. Indirect control transfer instructions can not be chained through only the software approaches. In this dissertation we propose a hardware support called ITTB which saves the translated target addresses of the frequently executed indirect control transfer instructions. ITTB are accessed during the execution of the translated indirect control transfer instructions thus enables a kind of dynamic chaining. The ITTB based method can also significantly improve the steady execution performance of a Co-VM.We design and implement a Co-VM protype called TransARM. The source architecture is IA-32 (a typical CISC architecture) and the target architecture is ARM (a typical RISC architecture). TransARM is used to evaluate the proposed Co-VM model and algorithms of this dissertation. We also discuss several critical issues in the implementation of a real Co-VM.