Design And Implementation Of Co-designed Dynamic Binary Translation System

The Dynamic Binary Translation (DBT) Technology was originally used to solve the binary compatibility problem between two different architectures. It was subsequently used in design of Virtual Machines (VM), and become a important basic technology in implementation and improve the performance of VMs. Nowadays, the DBT technology is playing a important role in virtualization of systems of different scales such as PC, server and embedded systems, etc. It has been successfully used in power management, security, software cache management, instruction set translation and memory management, etc. However, the traditional DBT systems based on software have some intrinsic defects such as high translation cost and low efficiency in code cache management. Besides, the arrival of multi-core platform brought new challenges to the existing DBT technology. To fully exert the superiority of the multi-core platform with DBT technology is the focus of the DBT system designersThe Co-designed DBT system can overcome the defects of the traditional DBT systems. It use customized special hardware to do some common functions, such as list checking, cache management. Therefore it improved the performance of the whole system. Based on the research of existing DBT technologies, the thesis explored the approaches of implementing a Co-designed DBT system on a heterogeneous multi-core platform. The main contributions are as follows:1) We proposed a new Co-designed DBT system model: CDBTS. It runs a software execution module on the object processor, and runs a translation module on a customized special co-processor. It also includes a series of hardware logic of list checking, cache management, etc. Therefore it has a higher performance and better flexibility.2) We designed and implemented a DBT VMM based on page fault mechanism. It can catch the page fault in code segment of user program, and achieve the functions of execution monitoring, untranslated code catching and forwarding, translated code linking, etc. It can be easily transplanted to different object platforms, greatly improved the flexibility of CDBTS.3) We customized a code cache based on dual port RAM for CDBTS. The cache can reduce the access collision of the two processors, and insure the coherence. We studied the strategies of code cache management, and implemented two hardware modules to improve the code cache management.4) We proposed a dynamic binary optimization framework for multi-threads based on multi-core platform. We analyzed the advantages and disadvantages of several existing typical dynamic binary optimization systems, considered the characters of dynamic binary optimization on multi-core platforms, and proposed a dynamic binary optimization framework for multi-threads based on multi-core platform. We also go on research in the feasibility of the implementation of the framework, and the unification of the CDBTS and the framework.To prove the availability of our work, we designed and implemented a Co-designed DBT prototype system: CDBTS-X2A based on our work. The CDBTS-X2A has IA-32 source architecture and ARM target architecture. It can be used as a research platform of Co-designed DBT system.