Research On Grid Memory Service Architecture

With development of network and digital media technology, computing and data to be processed increase quickly, and this requires more to computer's ability. With coming era of high frequency of IC and multi-core, it's difficult for computer's frequency to increase, and memory bottle neck becomes more serious. At the same time, tight coupling among processor, memory and disk makes it difficult to share resources, witch limits system performance and increases system cost. Dynamic Self-organized Computer Architecture based on Grid-components (DSAG) departs computer components to grid components to break the tight coupling, and dynamically aggregator and organize the components according to application's demand to realize architecture-on-demand. With development of optical interconnect and reconfigurable computing, it's possible to implement sharable girded memory components.From view of application's feature, data intensive and network intensive applications are increasing quickly, and overhead of data transfer has exceeded overhead of computing, as well as has characteristics of data-driven. From view of technology, chip area of logic circuit becomes much smaller than memory, and function customization is much easier than memory. So we can think that feature of"small computing, big memory"is becoming more obvious, and CPU centered design principle is possibly changed to memory centered design and optimization.This thesis proposed a Girded Memory Service based computer architecture; witch is based on DSAG and application feature as well as technology trend, and also developed a memory server named as Memory Box or Box.(I) proposed an architecture model based on Girded Memory Service (GMS), which assigns memory component with grid feature, and makes GMS as center of system design, optimization and application. Features of memory services include independence of demander and supplier, dynamically request and response, guaranteed by quality of service, and uniform interface and access mode. It solves the problems cause by tight coupling between memory and CPU, to improve system performance and decrease cost. The thesis described application modes of GMS, including memory-centered application mode, expanding local physical memory, replacing disk swap, improving DSM performance, and fast checkpoint. This thesis analyzed key technologies of GMS; including service mode and programming model, scalable architecture design, interconnect protocol and network, intelligent memory management and latency tolerance. Using Memory Box as target, this thesis researches these key technologies.(II) Analyzed Box's access interface and programming model. To realize memory service semantic and uniform access interface, we defined Girded Memory Access Protocol (GMAP) and implemented a programming library Glib. To adapt vary application, access port implement transfer between client network protocol and Memory Box internal interconnect protocol. We design and implement a reconfigurable verification system"Raindrop", to verify the feasibility of using memory bus as access interface to implement remote memory access."Raindrop"can transfer DDR RAM specification to user-defined interconnect protocol. At DDR200, hardware bandwidth reaches 10Gbps, very close to memory bandwidth; user level communication bandwidth can reach 285MB/s above, close to the result tested by benchmark.(III) Because memory has rigid demand to bandwidth and latency and needs to support multi-user concurrent access and intelligent memory management, components between CPU and Memory Box, and internal components inside Box require high speed, high density, high scalability and low cost interconnect. This thesis analyzed composite of latency, and According to the analysis result, this thesis researches removing latency effect by two ways. It design and impalement a high bandwidth, low latency, light weight, serial and packet switching interconnect protocol called Girded Memory Interconnect Protocol (GMIP). It optimized the link and physical layer of the protocol to take advantage of very short reach optical interconnect technology. Focusing on high bandwidth characteristics of optical interconnect and requirement of GMS, we studied interconnect effect, and proposed evaluation principle of bandwidth-latency compensating.(IV) In GMS, with rich and cheap embedded processors and control logic, we can realize intelligent memory, which can reduce pressure on memory bus, remove memory bottle neck, and hide latency. Active memory model is proposed and verified. Inter-level memory management and optimization is studied here. With typical application, verification and compurgation proved effectiveness of the technologies.(V) Designed and developed a Memory Box prototype. The access latency can reach us level. By test and evaluation, proves that Box can have superiority than disk swap, and active memory has superiority than non-active memory.