Analytical Modeling Of Memory Access Latency For DDR SDRAM

When analyzing the overall performance of the processor,the penalty time caused by the last-level cache miss--DDR SDRAM access latency accounts for a large proportion of the overall execution time.Therefore,the accurate evaluation of the memory access latency is particularly important for evaluating the performance of the system.Since cycle-accurate simulation is too time-consuming,analytical modeling of DRAM systems has become an effective choice to guide the optimization of the architecture.Some analytical models predict the DDR SDRAM access latency by taking the ratio of different DRAM command combinations,which requires a lot of analysis and a lot of time.Some other studies evaluate the DDR SDRAM access latency based on the queuing theory,but the accuracy is not high.This thesis find the regularity of the access latency through the measured data and propose an analytical model of DDR SDRAM access latency out of the simulation,which can quickly and accurately estimate the DDR SDRAM access latency.The DDR SDRAM access latency model proposed in this thesis is mainly composed of three parts:(1)the latency of transmitting the LLC misses on the bus or the interconnect architecture;(2)the time of transmitting the LLC misses in the DDR SDRAM controller;(3)The time when the LLC misses is served by DDR SDRAM.The time that the LLC misses is served by the DDR SDRAM is composed of the service latency of the DDR SDRAM read access request itself and the queuing latency in the DDR SDRAM.The phenomenon of the “three peaks” distribution of DDR SDRAM is proposed for the first time in this thesis.After detailed derivation of the principle and experimental verification,it is proposed that the queuing latency is due to waiting for the service process of the DDR SDRAM writes.17 benchmarks have been used to evaluate the accuracy of the DDR SDRAM access latency model.Compared with the simulation results of Gem5+DRAMSim2,the average error of the model is below 7%.The average error of the LPDDR SDRAM access latency model is 2.90%.In terms of time overhead,the model can save up to 95.56% runtime than that of cycle-accurate simulations.