Research On Performance Estimation Of SoC On-Chip Bus

Higher performance of the on-chip interconnection is needed because of the improvement of the system-on-chip integration and application requirements. On-chip bus is the main interconnection structure used in the current system-on-chip; it makes a target of high performance, low power dissipation and low hardware spending. In order to make the best choice of the on-chip bus structure, performance estimation is a quite significant and obligatory work. This paper focuses on performance estimation of the embedded microprocessor based on the on-chip bus, including on-chip bus modeling, high-level simulation environment building and their combination.The first part of this dissertation addresses the performance estimation based on the queuing network model and the high-level simulation model. Other than departed researches, more accurate queuing network models are established in allusion to a microprocessor named Garfield4. At the same time, high-level simulation environment based on C++ and instruction-level simulator– ARMulator has been build for system-level analysis. According to other similarly simulation environment, the analysis based on ARMulator has some obvious advantage such as easy, celerity and nicety. Furthermore, the hardware models have been building and the software can be debugged directly in ARMulator. Experiment results show that the performance estimation based on the queuing network model and the high-level simulation model is accurate and effective. The proposed method makes the quantificational and qualitative analysis and it can provide valuable reference for the designers.Then several applications of the performance estimation are finished by the proposed model, including bus buffer size evaluation, bus arbitration structure contrast, DMA integration choice and the performance estimation of the two-layer AMBA structure. In bus buffer size evaluation, the difference between the results based on the high-level simulation and the RTL simulation is less than 1%. And the queuing network analysis also finds the correct results. The experiments according to different bus arbitration algorithms indicate that the turn-around priority algorithm is the best choice. The analyses about DMA integration show that the performance could be improved obviously with adopting the appropriative DMA peripheral bus structure. In order to achieve the trade-off of the system performance, DMA single transfer's number should be considered carefully. Relative to the single layer bus structure, the mean wait time of the masters can decrease at least 50% in the two-layer AMBA structure. And the analysis based on the queuing network is close to the analysis based on the simulation. All of the above analyses indicate that the performance evaluation of the on-chip bus can be accomplished by the combined method, which includes queuing network analysis and high-level simulation analysis.On-chip bus modeling and the performance estimation method are offered in this paper. Firstly, advance the on-chip bus modeling, including analytical model and simulation model. Secondly, make the performance analysis of the on-chip bus structure in Garfield4. At last, a summary is given and some pursued problems about on-chip bus performance estimation are pointed out.