Model,Simulation,and Acceleration For NoC System-level Workability

As more and more components are integrated into a single chip,the yield issue of a Network-on-Chip system emerges,due to the large scale integration.On the other side,the tradition yield analysis is not sufficient to predict whether a Network-on-Chip system will work or not in runtime.Thus,this work proposes a new concept workability,which integrates details in different levels in a Network-on-Chip system,such as the mapping algorithms in application level,the routing strategies in architecture level,and the yield and defect details in physical level.The new workability concept is more realistic than the traditional yield,in terms of describing the runtime scenario of a Network-on-Chip system.To evaluate the workability of a Network-on-Chip,the Monte Carlo method is used,which is a time-consuming method.Thus,this work further explores the acceleration techniques for Monte Carlo method.Two acceleration techniques are proposed in this work:1)Accelerating by utilizing the parallel execution capability of a GPU platform,as well as the heterogeneous parallel capability between a GPU and a CPU;2)Accelerating by adopting Gibbs sampling in mathematical statistics,which can reduce the number of samples required in the Monte Carlo method.An optical Network-on-Chip is more energy-efficient,in terms of communication,than an electronic Network-on-Chip,if power tuning techniques are used.To reduce the power consumption in an optical Network-on-Chip,this work proposes a dynamic optical power scaling technique,which dynamically scales,even turns off,the optical link,according to the communication requirement.