Research On Key Optimization Technologies Of Binary Translation For The Domestic CPU

With the diversification of computer processors,new processors have more advanced design concepts and effective.But the lack of application software hinders the promotion of the processor.An important way to migrate software to a new processor is binary translation.Binary translation reduces the difficulty of migrating programs between different processors and expands the scope of processor,which is of great significance for the development of new domestic processors.However,dynamic binary translation is inefficiency and how to improve translation efficiency is a hot issue.The paper relies on major special subject and continues to previous work on the QEMU translation system,which focuses on the key optimization technologies of QEMU dynamic binary translation to improve the translation performance.In this paper,new optimization methods for QEMU System were proposed through the deep analysis of the X86 processor to a new domestic processor binary translation process.The main research and innovation include:1.The key technologies and implementation mechanisms for QEMU systems were summarized in the process of translating domestic processors,including operating principles and TCG keytechnologies.Meanwhile,QEMU binary translation was analyzed to explore possible optimization opportunities.On this basis,it proposed an optimization framework for domestic processor translation systems.2.The floating-point instruction translation process in QEMU was analyzed in detail and found that the floating-point register simulation mechanism and the helper function mechanism make translation of floating-point instruction appear to degrade performance,where with great optimization space.Therefore,it proposed floating point Optimize key technology,including floating point register mapping,floating point function simplification and floating point function localization,which can take full advantage of the local platform to achieve the efficient handling of floating-point instructions.3.The mechanism of QEMU system to deal with SIMD instruction was studied and confirmed that the frequent function call and function redundancy operation of QEMU system is the reason why SIMD instruction translation performance is inefficient.For this situation,the optimization method of SIMD instruction translation is proposed to face the issues.The optimization method allows the system to generate SIMD instructions for the same local function by using the newly introduced vector intermediate representation and modifying the HELPER call function which has been implemented in QEMU.Optimization scheme can significantly reduce the back-end generation code redundancy and the function of the translation call switch,as well as improving the efficiency of translation.The correctness and some modules of the optimization performance were tested based on Nbench and SPEC2006 benchmark.The experiments show that: The key optimization techniques proposed in this paper are correct,efficient and feasible.Optimization played a key role to improve the efficiency of translation.