The Study On The Design And Key Process Of InGaAs MOSFET On Flexible Substrate

Moore’s Law predicts that silicon-based CMOS will reach its physical limit, while InGaAs is a very promising channel material for the next generation CMOS device and related circuit design aiming at high speed and low consumption application since it owns superior electrical properties including high electron mobility, large electron saturation velocity, low subthreshold swing, high drive current, and flexible bandgap adjusted by its In content. Since conventional fabrication of III-V based devices is of high cost, it will dramatically reduce the manufacturing cost if the integration of InGaAs MOSFET with inexpensive flexible substrate is realized. Meanwhile, high performance inorganic based devices can be bendable and adjusted to non-planar working conditions unbrokenly. Flexible inorganic based devices with high performance are more portable, more intelligent and nearer onto human body. This dissertation focuses on the device structure design, optimization of critical fabrication process, and device fabrication for realizing InGaAs MOSFET transferred onto flexible substrate, and the main contributions are as follows:1. The physical model to characterize the high-K/III-V interface and the related circuit model have been established. It has been theoretically analyzed that the interface state density (Dit) can be extracted by using high frequency Terman method.2. The physical and electrical properties of high-K/GaAs MOS capacitor have been systematically investigated. A thin ZnO layer as the passivation layer on N-GaAs has been deposited using atomic layer deposition (ALD) and Al/Al2O3/ZnO/n-GaAs MOS capacitor has been successfully fabricated. The interface quality of N-GaAs MOS capacitor has been physically and electrically characterized by comprehensive measurements involving HRTEM, C-V, and XPS. The obtained results indicate that ALD a thin layer of ZnO prior to the deposition of Al2O3 can remarkably reduce the formation of low K arsenic and gallium oxides thereby improving the interface quality distinctly.3. We investigate the effect of ALD growth temperature and post deposition annealing (PDA) temperature on the interfacial and electrical characteristics of HfO2/p-GaAs MOS capacitor in detail. High-K dielectric HfO2 has been deposited under different ALD temperatures of 200,250, and 300℃, respectively. The measured results indicate that the low K arsenic and gallium oxides decrease evidently at the interface. Meanwhile, the "stretch-out" effect in C-V characteristics decreases and the values of flat-band voltage difference (△VFB) and hysteresis voltage (VH) fall off, indicating good interface quality. Ⅰ-Ⅴ measurements show that the major gate leakage current transport mechanism in III-V MOS capacitor is different when changing the ALD temperature. At temperatures of 250℃ and below, Frenkel-Poole dominates the leakage current transportation. However, at 300℃, Schottky emission is the major factor in contributing to the gate leakage current decline. By comparison of I-V characteristics of MOS system annealed at temperatures ranging from 400-600℃, the lowest leakage current has been obtained at 500℃ annealing for the dielectric deposition at 300℃. XPS measurements further demonstrate that arsenic oxides at the high-K/GaAs interface drops substantially. However, the content of Ga2O3 increases notably, indicative of an exchange reaction of GaAs and arsenic oxides forming Ga2O3. Therefore, characterization and optimization of high-K/GaAs MOS interface is the fundamental basis on the fabrication of high performance low In content InxGa1-xAs surface channel MOSFET.4. The GaAs nanomembrane has been modelled by COMSOL software based on the real device structure to determine its flexibility as well as bendability on the flexible substrate. For the case that GaAs nanomembrane is transferred onto PET substrate, when the degree of the bending of PET exceeds three times its thickness, the first, second, and third principle strain are all below the fracture strength of GaAs (2.7 Gpa). The simulation results show that non-organic devices fabricated on extremely thin GaAs nanomembrane can be well flexible. In this case, the epitaxial device structure can be realized for the flexible InGaAs MOSFET. Optimization of undercut process as well as the removal of insoluble residues by developer MF 321 lead to the successful lift-off of InGaAs(12nm)/GaAs(285nm)/InGaAs(12nm) nanomembrane from the rigid substrate.5. The flexible In0.2Ga0.sAs MOSFET design and critical fabrication processes have been comprehensively investigated. The device layout and process flow are firstly proposed. Non-alloyed ohmic contact has been designed to be Ti(20nm)/Pd(40nm)/Au(200nm) with the values comparable with Peide Ye’s work. Optimization of dry etching of etching hole patterns makes the sacrificial layer of AlGaAs expose to the subsequent wet etchig etchants. Shear strain assisted transfer has been applied to make the InGaAs/GaAs/InGaAs nanomembrane transferred onto PET substrate successfully.6. The first bendable InGaAs surface channel MOSFET on PET substrate is presented in this dissertation. The preliminary electrical measurements demonstrate that InGaAs flexible MOSFET can achieve the maximum drain current of 1μA/mm with the gate length of 2μm, gate width of 10μm, and 10nm Al2O3 as the gate dielectric. Meanwhile, the gate leakage current about 10-12 A has been observed, demonstrating the good insulation of Al2O3 deposited by ALD.