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Research On Interfacial Properties Of In InGaAs MOSFET Devices With Gate Dielectrics

Posted on:2020-01-21Degree:MasterType:Thesis
Country:ChinaCandidate:X LiFull Text:PDF
GTID:2428330599959732Subject:Engineering
Abstract/Summary:PDF Full Text Request
Traditional Silicon-based MOSFET devices are the basis for the development of modern integrated circuits.With the feature size of MOSFET devices continues to shrink,it is closed to the development of physical limits,such as source-drain tunneling effects,mobility reduction and other constraints on MOSFET device performance.The problem of improvement has caused the development of Moore's Law to slow down.III-V compound semiconductor materials have become one of the hot point in the research field of next-generation high-performance integrated circuits due to their high electron mobility,low leakage current and good resistance to breakdown.However,the interface quality of III-V semiconductor materials and high-k gate dielectrics is far below the level of MOSFET devices,and there are many problems that restrict the performance of III-V MOSFET devices.This paper focuses on improving the interface quality between high-k gate dielectric Al2O3 and InP substrate.The main research contents include:1.The surface of InP was treated by nitrogen plasma passivation process and sulfur passivation process.The interface characteristics of Al/Al2O3/InP metal oxide semiconductor?MOS?capacitors were investigated at 150 K.The sulfur passivation process can effectively reduce the interface dangling bond and reduce the fast interface state,and obtain the minimum interface state density of 1.6×1010 cm-2eV-1 at 150 K.2.The interface characteristics and gate leakage characteristics of N2-plasma passivated samples and sulfur passivated sample capacitors were analyzed at 150 K,200 K and 300 K test temperatures.Compared with the sulfur passivation process,the nitrogen passivation process can effectively improve the boundary defect density and reduce the slow interface state from 1.1×1012 cm-2V-1 to 5.9×1011 cm-2V-1,which is reduced with the increase of test temperature.At the same time,the leakage of trap tunneling decreases.3.Based on the above research,the device simulation model is optimized and improved by experimental measurement data.The influence of interface trap on the electrical properties of InP-based InGaAs channel MOSFET devices is investigated.Compared with the interface state obtained without passivation treatment,the output current and the saturation drain current Ids VDS=0.5 V for the sulfur passivation sample are increased by 249 mA/mm and 251 mA/mm,the N2-plasma passivation sample are 136mA/mm and 137 mA/mm,the maximum increase of transconductance peak is about 147mS/mm.Which indicates that the surface passivation process can effectively reduce the interface state density at the interface and reduce the scattering effect of carriers in the channel,thereby increasing the drive current and gate control capability of the device.
Keywords/Search Tags:interface trap density, border traps, gate leakage current, ?-? MOSFET
PDF Full Text Request
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