Simulation On Electrical Characteristics Of In InGaAs MOSFET And Interface Properties Of GaAs-La-Based High-k

With silicon-based MOSFETs move toward nanometer-scale,the size of the devices is shrinking,which will gradually approach the physical limits of Si-based materials.Therefore,new materials have to be used to solve some defects caused by the further reduction of the Si-based material,III-V compound materials?such as GaAs,InGaAs?have drawn much attention due to their higher carrier mobility.Among those materials,the electron mobility of GaAs as high as 8000cm²/Vs,so it is considered to be used to make low-power,high-speed MOSFET.In the new structure,the buffer layer structure can well solve the problem of lattice matching between the substrate and the channel layer,thus improve the channel quality and improve the device performance.In the part of the theoretical model,we use Silvaco software to simulate the electrical characteristics of high-k gate dielectric InGaAs MOSFETs with buffer,and then optimize the structure of the device.In the experiment,based on La-based high-k gate dielectric GaAs MOS,the effects of the cap layer,annealing temperature and other factors on the interfacial and electrical properties of the devices were investigated.Theoretically,high-k gate dielectric InGaAs MOSFETs with buffer is constructed by Silvaco TCAD software,then the electrical characteristics are simulated and the reasonable structural parameters are determined according to the simulation results to optimize the device structure.The short channel effect?SCE?,drain-induced barrier lowing?DIBL?effect is reduced by changing the relevant physical parameters such as channel thickness,channel length,channel doping concentration,gate oxide dielectric constant,and equivalent oxide thickness,thus reduce their impact on the electrical characteristics of the device as well as to obtain a larger on current(I_on)and smaller off current(I_off),through the comparison of different parameters to determine the reasonable structural parameters.The simulation results show that the thickness and length of the channel layer should be 5-7nm and 37-46nm respectively,the channel doping concentration should be?3-9?×10¹⁷cm^-3,and the equivalent oxide thickness is 0.8-1nm,Gate dielectric constant should be taken15-50.The main work in the experiment is as follows:?1?La₂O₃ was used as a high-k gate dielectric,to disscuss the influence of the presence or absence of capped Al₂O₃ and the high-k gate dielectric doped with N on the interfacial and electrical properties of GaAs MOS devices was investigated.Then,by studying the annealing temperature after deposition,the rationality of the annealing temperature adopted in the above experiment was confirmed.The experimental results show that the cap layer and the high-k gate material doped with N and 600?deposition annealing can get lower interface state density and gate leakage current,which can effectively improve the interface characteristics of GaAs MOS.?2?The effect of different oxide materials as cap layer and cap layer thickness on the performance of the device was studied.HfO₂ as the cap layer can get better electrical properties than ZrO₂ as the cap layer,and at the same time,the optimal cap layer thickness of 2 nm.