Calibration-free Low-power 12-bit 100MS/s ADC Design And Realization

High-speed high-resolution ADC is widely used in communication, data acquisition, ultrasound, audio and video fields, etc. With the rapid development of modern communication and SoC, the ADC is not only required to have high-speed high-resolution, but also have high static and dynamic performance, for simplifying the system design and lowering the cost purpose. Besides, SoC application requires its sub macros easy for integration and to be used as universal IPs. Under such demand, the ADC should be implemented in standard CMOS process with a few ports and wide application.Pipeline ADC can meet the speed, accuracy and power trade-off among all ADC algorithms. CMOS technology can offer high-performance switching device so more and more researches focus on switch-capacitor pipeline ADC in SoC design, which offers high dynamic and static performance. Calibration circuit will consume a certain physical area and power, so the calibration is not suitable for SoC application. As above mentioned, the research of low-power calibration-free pipeline ADC is necessary for the SOC application.The content of this thesis includes the design of high-linearity, low-power ADC and the key building blocks.1. A proposed charge-sharing correction circuit can compensate the charge loss due to the sharing effect between the bootstrapped capacitor and gate-source capacitance of switch transistor without affecting the overall frequency response of the whole ADC. The addition of the charge-sharing correction circuit can greatly enhance the linearity of the front-end sampling of the ADC, reduce the THD. The simulated results show that the THD increases by 10 dB when the charge-sharing correction is enabled compared to the disabled one. Based on the traditional common-centroid capacitor layout technique, an improved structure is proposed by matching the parasitic parameters to increase the matching accuracy of the capacitors. The implementation and measurement results of the final three-version ADC chips prove the effectiveness of the improvement.2. Various low-power techniques of pipeline ADC are analyzed, especially the defects and merits of SHA-less structure and opamp-sharing schemes are compared and studied thoroughly. The ADC in this doctoral thesis adopts SHA-less and opamp-sharing structure to greatly reduce the power dissipation and provide a way to eliminate the associate memory effect. A short reset pulse between the sample and the hold phase is proposed to cancel the kickback from MDAC stage and clear the input of the shared amplifier.3. For the pipeline ADC building block design, a high-gain high-bandwidth operational transconductance amplifier(OTA) is the key and most power-hungry unit in the pipeline ADC. A single-stage OTA with only one gain-boosting amplifier is proposed to ensure required bandwidth and open-loop gain within reasonable power dissipation. As the topology of the gain-boosting amplifier is the same as the main OTA, it is much easier to control its pole location to avoid pole-zero doublet effect. The reference generation circuit, including the bandgap reference and fully differential reference buffer is proposed to settle much faster than the conventional reference buffers. Besides, the noise and its relationship with the output impedance of the reference buffer are also analyzed. A thorough study of kick-back noise from latch comparator is carried out and a novel comparator clock scheme and high-speed latch structure is improved to reduce the kick-back noise from 42 mV down to 100μV and increase operating speed of the comparator respectively within a reasonable power dissipation.4. In order to verify the above innovations, three versions of the switch-capacitor pipeline 12-bit 100MS/s ADCs are implemented in 0.18μm 1P6 M CMOS technology. Version 1 utilizes the conventional 10×1.5bits/s+2bits pipeline structure and the improved common-centroid capacitor layout; version 2 uses the proposed 4bits+7×1.5bits/s+2bits pipeline structure and the conventioanl common-centroid capacitor layout; version 3 uses the proposed 4bits+7×1.5bits/s+2bits pipeline structure and the improved common-centroid capacitor layout. Five sample chips of each version are taken for measurement. The test results indicate that under the same test condition, version 1 has poorer linearity performance and comparably larger power dissipation than version 2. Version 3 also uses the proposed pipeline structure as version 2, so its power dissipation is close to version 2. And version 3 uses improved common-centroid capacitor layout other than version 2, so the linearity of version 3 is higher than version 2. The SFDR of version 3 is higher than the reported calibration-free ADC. The FoM of the ADC based on proposed techniques of this doctoral thesis is larger than some ADCs using advanced low-power techniques and technologies, but lower than the reported calibration-free 12-bit high speed ADCs, which proves the effectiveness of the proposed high linearity pipeline structure and low-power technique. The measure results show that the proposed ADC with multi-bit first stage, charge-sharing compensation, improved common-centroid capacitor layout techniques and the op-amp sharing and SHA-less combined structure can achieve comparable performance with the reported digital post-calibrated 12-bit 120MS/s ADC, without any calibration or trimming and only consumes a reasonable power.The proposed calibration-free ADC, which has fewer ports and is easy for universally use, can shorten the customization time. Meanwhile, owing to the proposed calibration-free and trimming-free structure,the presented ADC can cover various applications occupying only a small chip area, is more suitable for SoC application compared to the calibrated ADC. So the research of this doctoral thesis can virtually provide a way for ADC IP technique.