Research On High Speed,High Accuracy And Low Power Pipeline ADC

Accompanied by the development of electronic technology and information technology,electronic devices are also increasing.And these electronic products often need high-speed,high-precision analog-to-digital converters.IThere is a conversion from analog interval to digital interval in video decoder chip,So we need a high performance ADC.With the high-performance analog-to-digital converter,its circuit design is more difficult,the design cycle will be very long.So we conduct behavioral level modeling and system design before circuit design.The article first analyzed various analog-to-digital converters,determined the right analog-to-digital converter:Its precision is 10 bits,sampling rate is 100MHz.Then analyze the entire structure and working principle of the pipelined ADC,Included sub-modules are:sample-and-hold circuit,MDAC circuit,sub-ADC circuit and delay correction circuit.Based on this,we study and analyze the non-ideal factors in pipeline ADC,Mainly includes noise and error.The noise is mainly composed of switched capacitor thermal noise and operational amplifier thermal noise.The errors mainly include the limited gain error,clock jitter error and capacitance mismatch error of the op amp.This article analyzes and analyzes the power consumption of pipelined ADC.reducing power consumption while introducing capacitive reduction technology,The capacitance reduction in the case of trade-off noise and power consumption is therefore 0.8.At the same time,it also determines the structure of the entire assembly line,the first seven stages of the pipeline are 1.5.The last stage is a 3-bit flash ADC.After theoretical analysis,modeling the entire pipelined ADC.First model theideal submodule of the entire pipeline analog-to-digital converter.According to theoretical derivation and analysis,a noise model and various error models for pipelined ADCs are established.After completing each sub-module and delay calibration module into a complete pipelined ADC,plus noise and error modules.Then simulate the entire pipelined ADC,The dynamic parameter,ENOB is 9.308 bit,SNDR is 57.7942 dB,SNR is 64.2623dB,and SFDR is 63.3893dB.The DNL is-0.157?0.05 LSB,and the INL is-0.77?0.58 LSB.